Inventor
Michael S. Briner
Inventor
San Jose, CA, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores63%
H03KPulse technique13%
G05FSystems for regulating electric or magnetic variables8%
H10BElectronic memory devices5%
H03GControl of amplification3%
G06FElectric digital data processing2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
8,369,115'Time domain voltage step down capacitor based circuit'20137,184,345'High speed and high precision sensing for digital multilevel non-volatile memory system'20077,038,960'High speed and high precision sensing for digital multilevel non-volatile memory system'20066,996,010'Fast-sensing amplifier for flash memory'20066,944,064'Memory unit having programmable device ID'20056,914,822'Read-biasing and amplifying system'20056,885,600'Differential sense amplifier for multilevel non-volatile memory'20056,788,608'High voltage pulse method and apparatus for digital multilevel non-volatile memory integrated system'20046,744,673'Feedback biasing integrated circuit'20046,529,409'Integrated circuit for concurrent flash memory with uneven array architecture'20036,525,967'Fast-sensing amplifier for flash memory'20036,396,739'Reference voltage generator using flash memory cells'20026,272,586'Memory system having programmable control parameters'20016,229,352'Power level detection circuit'20016,181,593'Memory array having a reduced number of metal source lines'20016,141,247'Non-volatile data storage unit and method of controlling same'20006,108,237'Fast-sensing amplifier for flash memory'20006,094,377'Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell'20006,046,615'Level detection circuit'20005,963,061'Switch for minimizing transistor exposure to high voltage'19995,953,256'Reference voltage generator using flash memory cells'19995,903,504'Op amp circuit with variable resistance and memory system including same'19995,896,400'Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell'19995,867,424'Memory array having a reduced number of metal source lines'19995,867,042'Switch for minimizing transistor exposure to high voltage'19995,864,499'Non-volatile data storage unit and method of controlling same'19995,862,077'Fast sensing amplifier for flash memory'19995,835,411'Computer including a fast sensing amplifier'19985,801,985'Memory system having programmable control parameters'19985,767,711'Level detection circuit and method'19985,757,697'Method for sensing the binary state of a floating-gate memory device'19985,721,702'Reference voltage generator using flash memory cells'19985,706,235'Memory circuit with switch for selectively connecting an I/O pad directly to a nonvolatile memory cell and method for operating same'19985,694,366'OP amp circuit with variable resistance and memory system including same'19975,682,345'Non-volatile data storage unit method of controlling same'19975,677,879'Method and apparatus for performing memory cell verification on a nonvolatile memory circuit'19975,631,864'Memory array having a reduced number of metal source lines'19975,619,150'Switch for minimizing transistor exposure to high voltage'19975,594,694'Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell'19975,581,206'Power level detection circuit'19965,579,274'Sense circuit for a flash eefprom cell having a negative delta threshold voltage'19965,568,426'Method and apparatus for performing memory cell verification on a nonvolatile memory circuit'19965,559,990'Memories with burst mode access'19965,477,499'Memory architecture for a three volt flash EEPROM'19955,231,602'Apparatus and method for improving the endurance of floating gate devices'19935,101,378'Optimized electrically erasable cell for minimum read disturb and associated method of sensing'19925,005,155'Optimized electrically erasable PLA cell for minimum read disturb'19914,935,648'Optimized E.sup.2 pal cell for minimum read disturb'19904,714,901'Temperature compensated complementary metal-insulator-semiconductor oscillator'19874,629,972'Temperature insensitive reference voltage circuit'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–1996Patents assigned to ADVANCED MICRO DEVICES INC (7)· patent assignee history
1986–2013Based in San Jose, CA, US· patent location history
1990Patents assigned to ADVANCE MICRO DEVICES INC (1)· patent assignee history
1996–1998Patents assigned to MICRON QUANTUM DEVICES INC (12)· patent assignee history
1998–2006Patents assigned to MICRON TECHNOLOGY INC (22)· patent assignee history
2003–2007Patents assigned to SILICON STORAGE TECH INC (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 22 | 1998–2006 |
| MICRON QUANTUM DEVICES INC | 12 | 1996–1998 |
| ADVANCED MICRO DEVICES INC | 7 | 1986–1996 |
| SILICON STORAGE TECH INC | 6 | 2003–2007 |
| ADVANCE MICRO DEVICES INC | 1 | 1990 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 50 | 1986–2013 |