Inventor
Ronald J. Syzdek
Inventor
Austin, TX, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores63%
G06FElectric digital data processing7%
H10BElectronic memory devices5%
H10DInorganic electric semiconductor devices5%
B82YSpecific uses or applications of nanostructures2%
G05FSystems for regulating electric or magnetic variables2%
G06NComputing arrangements based on specific computational models2%
H01LSemiconductor devices2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H03KPulse technique2%
PatentTitleYear
10,825,512Memory reads of weight values20209,837,161Split-gate memory having sector retirement with reduced current and method therefor20179,685,339'Scalable split gate memory cell array'20179,536,614'Common source architecture for split gate memory'20179,218,889'Multibit sense amplifier calibration'20159,111,639'Biasing split gate memory cell during power-off mode'20159,111,629'Smart charge pump configuration for non-volatile memories'20159,013,927'Sector-based regulation of program voltages for non-volatile memory (NVM) systems'20158,971,147'Control gate word line driver circuit for multigate memory'20158,885,403'Programming a split gate bit cell'20148,704,587'Configurable multistage charge pump using a supply detect scheme'20148,310,877'Read conditions for a non-volatile memory (NVM)'20127,865,797'Memory device with adjustable read reference based on ECC and method thereof'20117,843,730'Non-volatile memory with reduced charge fluence'20107,782,664'Method for electrically trimming an NVM reference cell'20107,742,340'Read reference technique with current degradation protection'20107,668,018'Electronic device including a nonvolatile memory array and methods of using the same'20107,649,781'Bit cell reference device and methods thereof'20107,624,329'Programming a memory device having error correction logic'20097,564,716'Memory device with retained indicator of read reference level'20097,545,679'Electrical erasable programmable memory transconductance testing'20097,259,999'Non-volatile memory cell array for improved data retention and method of operating thereof'20076,615,391'Current controlled multi-state parallel test for semiconductor device'20036,408,411'Two pass multi-state parallel test for semiconductor device'20026,381,718'Current controlled multi-state parallel test for semiconductor device'20025,694,073'Temperature and supply-voltage sensing circuit'19975,668,769'Memory device performance by delayed power-down'19975,646,894'Smart boost circuit for low voltage flash EPROM'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2003Patents assigned to TEXAS INSTRUMENTS INC (6)· patent assignee history
1997–2003Based in Sugar Land, TX, US· patent location history
2007–2017Patents assigned to FREESCALE SEMICONDUCTOR INC (20)· patent assignee history
2007–2020Based in Austin, TX, US· patent location history
2012–2017Patents assigned to SYZDEK RONALD J (9)· patent assignee history
2012–2015Patents assigned to CUNNINGHAM JEFFREY C (4)· patent assignee history
2017–2020Patents assigned to NXP USA INC (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 20 | 2007–2017 |
| SYZDEK RONALD Jself | 9 | 2012–2017 |
| TEXAS INSTRUMENTS INC | 6 | 1997–2003 |
| CUNNINGHAM JEFFREY C | 4 | 2012–2015 |
| NXP USA INC | 4 | 2017–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 22 | 2007–2020 |
| Sugar Land, Texas, US | 6 | 1997–2003 |