Inventor
Dae-Lok Bae
Inventor
Seoul, KR
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
G02BOptical elements, systems or apparatus14%
H10DInorganic electric semiconductor devices12%
H01LSemiconductor devices8%
H10BElectronic memory devices4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
H04BTransmission2%
PatentTitleYear
9,831,164Semiconductor device and method of fabricating the same20179,530,726'Semiconductor device and method of fabricating the same'20169,103,974'Semiconductor devices having optical transceiver'20158,958,002'Image sensors'20158,873,901'Buried-type optical input/output devices and methods of manufacturing the same'20148,867,882'Optical input/output device for photo-electric integrated circuit device and method of fabricating same'20148,791,405'Optical waveguide and coupler apparatus and method of manufacturing the same'20148,735,265'Methods of selectively forming silicon-on-insulator structures using selective expitaxial growth process'20148,570,409'Image sensors and methods of manufacturing image sensors'20138,546,162'Method for forming light guide layer in semiconductor substrate'20138,422,845'Optical input/output device for photo-electric integrated circuit device and method of fabricating same'20138,390,120'Semiconductor device and method of fabricating the same'20138,354,308'Conductive layer buried-type substrate, method of forming the conductive layer buried-type substrate, and method of fabricating semiconductor device using the conductive layer buried-type substrate'20138,343,851'Wafer temporary bonding method using silicon direct bonding'20138,324,055'Methods of manufacturing buried wiring type substrate and semiconductor device incorporating buried wiring type substrate'20128,319,329'Stacked integrated circuit package having recessed sidewalls'20128,129,833'Stacked integrated circuit packages that include monolithic conductive vias'20127,932,163'Methods of forming stacked semiconductor devices with single-crystal semiconductor regions'20117,781,302'Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions'20107,605,022'Methods of manufacturing a three-dimensional semiconductor device and semiconductor devices fabricated thereby'20096,437,445'Niobium-near noble metal contact structures for integrated circuits'20026,150,249'Methods of forming niobium-near noble metal contact structures for integrated circuits'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2017Patents assigned to SAMSUNG ELECTRONICS CO LTD (22)· patent assignee history
2000–2002Based in Kyungki-do, KR· patent location history
2009–2010Based in Gyeonggi-do, KR· patent location history
2011–2017Based in Seoul, KR· patent location history
2012–2016Patents assigned to BAE DAE-LOK (13)· patent assignee history
2012–2016Patents assigned to KANG PIL-KYU (13)· patent assignee history
2012–2016Patents assigned to CHOI GIL-HEYUN (8)· patent assignee history
2013–2015Patents assigned to PARK BYUNG-LYUL (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 22 | 2000–2017 |
| BAE DAE-LOKself | 13 | 2012–2016 |
| KANG PIL-KYU | 13 | 2012–2016 |
| CHOI GIL-HEYUN | 8 | 2012–2016 |
| PARK BYUNG-LYUL | 5 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seoul, KR | 18 | 2011–2017 |
| Gyeonggi-do, KR | 2 | 2009–2010 |
| Kyungki-do, KR | 2 | 2000–2002 |