Inventor
Sam Geha
Inventor
Sunnyvale, CA, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H10DInorganic electric semiconductor devices13%
G11CStatic stores12%
H01LSemiconductor devices10%
B82YSpecific uses or applications of nanostructures7%
C23CCoating metallic material6%
H10BElectronic memory devices6%
H01JElectric discharge tubes or discharge lamps1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
10,903,342Oxide-nitride-oxide stack having multiple oxynitride layers202110,903,068Oxide-nitride-oxide stack having multiple oxynitride layers202110,896,973Oxide-nitride-oxide stack having multiple oxynitride layers202110,374,067Oxide-nitride-oxide stack having multiple oxynitride layers20199,449,831'Oxide-nitride-oxide stack having multiple oxynitride layers'20169,355,849'Oxide-nitride-oxide stack having multiple oxynitride layers'20169,349,824'Oxide-nitride-oxide stack having multiple oxynitride layers'20168,643,124'Oxide-nitride-oxide stack having multiple oxynitride layers'20148,093,128'Integration of non-volatile charge trap memory devices and logic CMOS devices'20127,205,164'Methods for fabricating magnetic cell junctions and a structure resulting and/or used for such methods'20076,803,318'Method of forming self aligned contacts'20046,756,315'Method of forming contact openings'20046,756,302'Low temperature metallization process'20046,693,042'Method for etching a dielectric layer formed upon a barrier layer'20046,627,547'Hot metallization process'20036,534,398'Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit'20036,309,971'Hot metallization process'20016,187,667'Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit'20016,156,645'Method of forming a metal layer on a substrate, including formation of wetting layer at a high temperature'20006,140,228'Low temperature metallization process'20005,977,638'Edge metal for interconnect layers'19995,968,851'Controlled isotropic etch process and method of forming an opening in a dielectric layer'19995,339,039'Langmuir probe system for radio frequency excited plasma processing system'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2004Based in Sunnyvale, CA, US· patent location history
1999–2016Patents assigned to CYPRESS SEMICONDUCTOR CORP (17)· patent assignee history
2007–2021Based in Cupertino, CA, US· patent location history
2012–2016Patents assigned to GEHA SAM (3)· patent assignee history
2012–2016Patents assigned to LEVY SAGY (3)· patent assignee history
2012–2016Patents assigned to RAMKUMAR KRISHNASWAMY (3)· patent assignee history
2019–2021Patents assigned to Longitude Flash Memory Solutions Ltd (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CYPRESS SEMICONDUCTOR CORP | 17 | 1999–2016 |
| Longitude Flash Memory Solutions Ltd | 4 | 2019–2021 |
| GEHA SAMself | 3 | 2012–2016 |
| LEVY SAGY | 3 | 2012–2016 |
| RAMKUMAR KRISHNASWAMY | 3 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 13 | 1994–2004 |
| Cupertino, California, US | 10 | 2007–2021 |