Inventor
YI-WEN WU
Inventor
TW
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10DInorganic electric semiconductor devices5%
G01RMeasuring electric variables1%
H10BElectronic memory devices1%
PatentTitleYear
12,532,771Package structure with fan-out feature202612,525,556Semiconductor devices and methods of manufacture202612,476,198Package structure with adhesive element over semiconductor chip202512,412,857Hybrid micro-bump integration with redistribution layer202512,388,028Package structure202512,308,322Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same202512,308,313Semiconductor package with improved interposer structure202512,300,598Package structure and method of fabricating the same202512,237,262Semiconductor package with improved interposer structure202512,176,337Semiconductor devices and methods of manufacturing202412,094,819Method for forming package structure202412,051,654Package structure and method of fabricating the same202411,901,279Semiconductor package and method of manufacturing the same202411,901,277Semiconductor package and method of manufacturing the same202411,855,014Semiconductor device and method202311,855,028Hybrid micro-bump integration with redistribution layer202311,848,265Semiconductor package with improved interposer structure202311,824,007Dual-sided routing in 3D SiP structure202311,804,451Package structure and method of fabricating the same202311,637,054Semiconductor package and method of manufacturing the same202311,600,573Structure and formation method of chip package with conductive support elements to reduce warpage202311,594,484Forming bonding structures by using template layer as templates202311,430,776Semiconductor devices and methods of manufacturing202211,410,953Via structure for packaging and a method of forming202211,362,010Structure and formation method of chip package with fan-out feature202211,322,447Dual-sided routing in 3D SiP structure202211,302,650Package structure and method of fabricating the same202211,257,714Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same202211,239,233Integrated circuit packages and methods of forming same2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (29)· patent assignee history
2022–2026Based in TW· patent location history
2023Patents assigned to TAIWAN SEMICONDUCTOR MFG (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 29 | 2022–2026 |
| TAIWAN SEMICONDUCTOR MFG | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 29 | 2022–2026 |