LexDanaLexDanabeta
Inventor

Chin-Long Chen

Inventor
Fishkill, NY, US

Overview

67→
Patents
1977–2019
Patent span
Physics
Primary field (CPC G)

Patents· 67 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing40%
H03MCoding32%
G06KGraphical data reading9%
G11BInformation storage based on relative movement between record carrier and transducer3%
G11CStatic stores3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
A63BApparatus for physical training, gymnastics, swimming, climbing, or fencing1%
F01CRotary-piston or oscillating-piston machines or engines1%
F02BInternal-combustion piston engines1%
G05BControl or regulating systems in general1%
PatentTitleYear
10,291,258Error correcting code for correcting single symbol errors and detecting double bit errors20198,033,964'Dumbbell assembly'20117,904,195'Method for prognostic maintenance in semiconductor manufacturing equipments'20117,627,114'Efficient modular reduction and modular multiplication'20097,487,425'Low cost symbol error correction coding and decoding'20097,243,293'(18, 9) Error correction code for double error correction and triple error detection'20077,171,591'Method and apparatus for encoding special uncorrectable errors in an error correction code'20077,093,183'Symbol level error correction codes which protect against memory chip and bus line failures'20067,080,110'Hardware implementation for modular multiplication using a plurality of almost entirely identical processor elements'20067,028,248'Multi-cycle symbol level error correction and memory system'20066,978,016'Circuits for calculating modular multiplicative inverse'20056,963,645'Method for implementing the chinese remainder theorem'20056,963,977'Circuits and methods for modular exponentiation'20056,957,243'Block-serial finite field multipliers'20056,929,995'Method of forming high voltage metal oxide semiconductor transistor'20056,914,983'Method for checking modular multiplication'20056,804,696'Pipelining operations in a system for performing modular multiplication'20046,763,365'Hardware implementation for modular multiplication using a plurality of almost entirely identical processor elements'20046,751,769'(146,130) error correction code utilizing address information'20046,675,341'Extended error correction for SEC-DED codes with package error detection ability'20046,675,349'Error correction coding of data blocks with included parity bits'20046,539,513'Dual functioning symbol error correction code'20036,519,736'Generating special uncorrectable error codes for failure isolation'20036,463,563'Single symbol correction double symbol detection code employing a modular H-matrix'20026,460,157'Method system and program products for error correction code conversion'20026,457,154'Detecting address faults in an ECC-protected memory'20026,392,571'String search apparatus and method for data compression'20026,386,456'Memory card identification system'20026,179,207'Method for writing single width bar codes on semiconductors wafers'20016,044,483'Error propagation operating mode for error correcting code retrofit apparatus'20006,018,817'Error correcting code retrofit method and apparatus for multiple memory configurations'20006,009,548'Error correcting code retrofit method and apparatus for multiple memory configurations'19995,956,351'Dual error correction code'19995,907,671'Fault tolerant system based on voting'19995,805,615'Method and apparatus for encoding certain double-error correcting and triple-error detecting codes'19985,774,481'Reduced gate error detection and correction circuit'19985,768,294'Memory implemented error detection and correction code capable of detecting errors in fetching data from a wrong address'19985,761,221'Memory implemented error detection and correction code using memory modules'19985,757,823'Error detection and correction for four-bit-per-chip memory system'19985,754,562'Method and apparatus for encoding certain double-error correcting and triple-error detecting codes'19985,751,745'Memory implemented error detection and correction code with address parity bits'19985,745,507'Systematic symbol level ECC for use in digital memory systems'19985,691,996'Memory implemented error detection and correction code with address parity bits'19975,682,394'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'19975,631,915'Method of correcting single errors'19975,600,659'Low cost symbol error correction coding and decoding'19975,581,071'Barcode scanner with adjustable light source intensity'19965,581,567'Dual level error detection and correction employing data subsets from previously corrected data'19965,552,591'Presence/absence bar code'19965,537,427'Modular multiple error correcting code system'19965,537,431'Method and apparatus for bar code reading and decoding'19965,537,423'Modular multiple error correcting code system'19965,533,036'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'19965,521,709'Continuous barcode marking system'19965,425,038'Error plus single bit error detection'19955,380,998'Single width bar code with end code providing bidirectionality'19955,228,046'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'19935,161,163'Method and apparatus for providing error correction to symbol level codes'19925,070,504'Method and apparatus for providing error correction to symbol level codes'19915,058,115'Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature'19914,862,463'Error correcting code for 8-bit-per-chip memory with reduced redundancy'19894,661,955'Extended error correction for package error correction codes'19874,552,107'Rotary internal combustion engine'19854,509,172'Double error correction - triple error detection code'19854,464,753'Two bit symbol SEC/DED code'19844,142,174'High speed decoding of Reed-Solomon codes'19794,035,767'Error correction code and apparatus for the correction of differentially encoded quadrature phase shift keyed data (DQPSK)'1977

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1977–2009Patents assigned to IBM (62)· patent assignee history
1977–2001Based in Wappingers Falls, NY, US· patent location history
1985Patents assigned to CHEN CHIN L (1)· patent assignee history
1987–1991Based in Wappinger Falls, NY, US· patent location history
1995–2009Based in Fishkill, NY, US· patent location history
2011Patents assigned to CHEN CHIN-LONG (1)· patent assignee history
2011Patents assigned to INOTERA MEMORIES INC (1)· patent assignee history
2011Based in Taichung, TW· patent location history
2019Patents assigned to ADVANCED MICRO DEVICES INC (1)· patent assignee history
2019Based in South Windsor, CT, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM621977–2009
ADVANCED MICRO DEVICES INC12019
CHEN CHIN Lself11985
CHEN CHIN-LONGself12011
INOTERA MEMORIES INC12011
Locations
LocationPatentsSpan
Fishkill, New York, US471995–2009
Wappingers Falls, New York, US131977–2001
Wappinger Falls, New York, US21987–1991
South Windsor, CT, US12019
Taichung, TW12011