Inventor
BOON TEIK CHAN
Inventor
BE
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices31%
H01LSemiconductor devices23%
B82YSpecific uses or applications of nanostructures18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10BElectronic memory devices1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
12,527,079Method for forming a stacked FET device202612,519,015Conductive via formation connecting transistor structures in an integrated circuit202612,520,556Method for forming a semiconductor device202612,513,878Bit cell with isolating wall202512,484,289Method for forming a stacked transistor device202512,457,785Method for forming a stacked FET device202512,446,247Circuit cell for a standard cell semiconductor device202512,324,175FET device and a method for forming a FET device202512,237,371Method for forming a semiconductor device202512,237,207Method for forming a buried metal line in a semiconductor substrate202512,154,832Method for forming a semiconductor device and a semiconductor device202411,862,452Contact isolation in semiconductor devices202411,854,803Gate spacer patterning202311,824,122Method for filling a space in a semiconductor202311,682,591Method for forming transistor structures202311,638,391Method for processing a semiconductor device with two closely spaced gates202311,610,980Method for processing a FinFET device202311,545,401Isolated semiconductor layer stacks for a semiconductor device202311,527,431Methods of semiconductor device processing202211,488,826Self-aligned layer patterning202211,430,697Method of forming a mask layer202211,430,876Method for producing self-aligned gate and source/drain via connections for contacting a FET transistor202211,348,842Split replacement metal gate integration202211,335,597Method for forming a buried metal line2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to IMEC VZW (24)· patent assignee history
2022–2026Based in BE· patent location history
2025Patents assigned to UNIV LEUVEN KATH (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IMEC VZW | 24 | 2022–2026 |
| UNIV LEUVEN KATH | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| BE | 24 | 2022–2026 |