Inventor
Stuart A. Sieg
Inventor
Albany, NY, US
Overview
Patents· 55 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices28%
H10DInorganic electric semiconductor devices24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B82YSpecific uses or applications of nanostructures2%
G06FElectric digital data processing1%
H01JElectric discharge tubes or discharge lamps1%
H10BElectronic memory devices1%
PatentTitleYear
11,121,024Tunable hardmask for overlayer metrology contrast202111,031,248Alternating hardmasks for tight-pitch line formation202110,985,025Fin cut profile using fin base liner202110,943,911Vertical transport devices with greater density through modified well shapes202110,832,919Measuring and modeling material planarization performance202010,811,508Vertical transistors having multiple gate thicknesses for optimizing performance and device density202010,811,507Vertical transistors having multiple gate thicknesses for optimizing performance and device density202010,741,452Controlling fin hardmask cut profile using a sacrificial epitaxial structure202010,734,372Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows202010,665,715Controlling gate length of vertical transistors202010,642,950Verifying planarization performance using electrical measures202010,629,489Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices202010,622,248Tunable hardmask for overlayer metrology contrast202010,580,652Alternating hardmasks for tight-pitch line formation202010,535,529Semiconductor fin length variability control202010,461,172Vertical transistors having improved gate length control using uniformly deposited spacers201910,410,875Alternating hardmasks for tight-pitch line formation201910,361,129Self-aligned double patterning formed fincut201910,312,103Alternating hardmasks for tight-pitch line formation201910,312,346Vertical transistor with variable gate length201910,304,744Inverse tone direct print EUV lithography enabled by selective material deposition201910,304,689Margin for fin cut using self-aligned triple patterning201910,249,753Gate cut on a vertical field effect transistor with a defined-width inorganic mask201910,242,952Registration mark formation during sidewall image transfer process201910,211,319Stress retention in fins of fin field-effect transistors201910,211,321Stress retention in fins of fin field-effect transistors201910,176,997Direct gate patterning for vertical transport field effect transistor201910,121,785Pitch scalable active area patterning structure and process for multi-channel fin FET technologies201810,121,852Structure and process to tuck fin tips self-aligned to gates201810,121,853Structure and process to tuck fin tips self-aligned to gates201810,103,022Alternating hardmasks for tight-pitch line formation201810,043,760Registration mark formation during sidewall image transfer process201810,032,680Strained finFET device fabrication20189,997,369Margin for fin cut using self-aligned triple patterning20189,917,019'Strained FinFET device fabrication'20189,882,048'Gate cut on a vertical field effect transistor with a defined-width inorganic mask'20189,876,074Structure and process to tuck fin tips self-aligned to gates20189,859,224'Registration mark formation during sidewall image transfer process'20189,842,737'Self-aligned quadruple patterning process'20179,812,324'Methods to control fin tip placement'20179,805,992'Strained finFET device fabrication'20179,805,991'Strained finFET device fabrication'20179,741,856'Stress retention in fins of fin field-effect transistors'20179,721,848'Cutting fins and gates in CMOS devices'20179,673,199'Gate cutting for a vertical transistor device'20179,589,958'Pitch scalable active area patterning structure and process for multi-channel finFET technologies'20179,502,411'Strained finFET device fabrication'20169,472,506'Registration mark formation during sidewall image transfer process'20169,305,845'Self-aligned quadruple patterning process'20169,293,375'Selectively grown self-aligned fins for deep isolation integration'20169,252,022'Patterning assist feature to mitigate reactive ion etch microloading effect'20169,209,178'finFET isolation by selective cyclic etch'20158,822,141'Front side wafer ID processing'20148,450,120'SEM repair for sub-optimal features'20138,211,717'SEM repair for sub-optimal features'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2021Patents assigned to IBM (53)· patent assignee history
2012–2013Patents assigned to NAFISI KOUROSH (2)· patent assignee history
2012–2013Patents assigned to SIEG STUART A (2)· patent assignee history
2012–2013Patents assigned to SOLECKY ERIC PETER (2)· patent assignee history
2012–2013Based in Hopewell Junction, NY, US· patent location history
2014–2021Based in Albany, NY, US· patent location history
2016–2017Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 53 | 2012–2021 |
| GLOBALFOUNDRIES INC | 2 | 2016–2017 |
| NAFISI KOUROSH | 2 | 2012–2013 |
| SIEG STUART Aself | 2 | 2012–2013 |
| SOLECKY ERIC PETER | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Albany, New York, US | 53 | 2014–2021 |
| Hopewell Junction, New York, US | 2 | 2012–2013 |