Inventor
Narasimha LANKA
Inventor
US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing38%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
H01LSemiconductor devices20%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
G06NComputing arrangements based on specific computational models2%
G11CStatic stores2%
H03KPulse technique2%
H03MCoding2%
PatentTitleYear
12,591,727Lane repair and lane reversal implementation for die-to-die (D2D) interconnects202612,554,672Link layer-PHY interface adapter202612,505,065On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY202512,499,019Retimers to extend a die-to-die interconnect202512,481,614Standard interfaces for die to die (D2D) interconnect stacks202512,468,597Valid signal for latency sensitive die-to-die (D2D) interconnects202512,405,912Link initialization training and bring up for die-to-die interconnect202512,362,306Clock-gating in die-to-die (D2D) interconnects202512,360,934Parameter exchange for a die-to-die interconnect202512,353,305Compliance and debug testing of a die-to-die interconnect202512,347,818Logic die in a multi-chip package having a configurable physical interface to on-package memory202512,332,826Die-to-die interconnect202512,321,305Sideband interface for die-to-die interconnects202512,316,343PHY-based retry techniques for die-to-die interfaces202512,181,966Reduction of latency impact of on-die error checking and correction (ECC)202412,117,960Approximate data bus inversion technique for latency sensitive applications202411,971,841Link layer-PHY interface adapter202411,954,360Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output links202411,599,497High performance interconnect2023Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2023–2026Patents assigned to INTEL CORP (19)· patent assignee history
2023–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 19 | 2023–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 19 | 2023–2026 |