Inventor
Emilio Camerlenghi
Inventor
Bergamo, IT
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices31%
G11CStatic stores24%
H10DInorganic electric semiconductor devices16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
G06FElectric digital data processing5%
H01LSemiconductor devices5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
PatentTitleYear
11,094,627Methods used in forming a memory array comprising strings of memory cells202111,011,236Erasing memory202110,950,316Apparatus for determining a pass voltage of a read operation202110,777,286Apparatus and methods for determining data states of memory cells202010,756,105Memory arrays and methods used in forming a memory array20209,214,389'Methods of forming memory arrays'20158,211,762'Non-volatile memory'20127,551,465'Reference cell layout with enhanced RTN immunity'20097,078,294'Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure'20066,944,061'Single cell erasing method for recovering memory cells under programming disturbs in non volatile semiconductor memory devices'20056,903,995'Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method'20056,750,505'Non-volatile memory cell with floating gate region autoaligned to the isolation and with a high coupling coefficient'20046,537,879'Process for manufacturing a non-volatile memory cell with a floating gate region autoaligned to the isolation and with a high coupling coefficient'20036,420,223'Manufacturing process for non-volatile floating gate memory cells integrated on a semiconductor substrate and comprised in a cell matrix with an associated control circuitry'20026,380,582'Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates'20026,376,306'Method for forming non volatile memory structures on a semiconductor substrate'20026,372,597'Method and a circuit for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor substrate'20026,284,585'Electronic memory device having bit lines with block selector switches'20016,242,793'Method and a circuit for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor'20016,222,245'High capacity capacitor and corresponding manufacturing process'20016,130,165'Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates'20006,124,169'Contact structure and associated process for production of semiconductor electronic devices and in particular nonvolatile EPROM and flash EPROM memories'20006,101,124'Memory block for realizing semiconductor memory devices and corresponding manufacturing process'20005,969,977'Electronic memory device having bit lines with block selector switches'19995,905,677'Voltage regulator for non-volatile semiconductor electrically programmable memory devices'19995,682,349'Failure tolerant memory device, in particular of the flash EEPROM type'19975,659,516'Voltage regulator for non-volatile semiconductor electrically programmable memory devices'19975,576,990'Voltage regulator for non-volatile semiconductor memory devices'19965,440,510'Integrated circuit entirely protected against ultraviolet rays'19955,330,938'Method of making non-volatile split gate EPROM memory cell and self-aligned field insulation'19945,241,499'Non-volatile split gate EPROM memory cell and self-aligned field insulation process for obtaining the above cell'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2001Patents assigned to SGS THOMSON MICROELECTRONICS (5)· patent assignee history
1993–2021Based in Bergamo, IT· patent location history
1996–2005Patents assigned to ST MICROELECTRONICS SRL (17)· patent assignee history
2009–2012Patents assigned to CAMERLENGHI EMILIO (2)· patent assignee history
2012–2021Patents assigned to MICRON TECHNOLOGY INC (7)· patent assignee history
2012Patents assigned to ALBINI GIULIO (1)· patent assignee history
2021Based in Bergamo (BG), IT· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ST MICROELECTRONICS SRL | 17 | 1996–2005 |
| MICRON TECHNOLOGY INC | 7 | 2012–2021 |
| SGS THOMSON MICROELECTRONICS | 5 | 1993–2001 |
| CAMERLENGHI EMILIOself | 2 | 2009–2012 |
| ALBINI GIULIO | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bergamo, IT | 30 | 1993–2021 |
| Bergamo (BG), IT | 1 | 2021 |