Inventor
Deepak D. Sherlekar
Inventor
Cupertino, CA, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing34%
H10DInorganic electric semiconductor devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H01LSemiconductor devices13%
H10BElectronic memory devices6%
G11CStatic stores3%
H03KPulse technique2%
PatentTitleYear
10,990,722FinFET cell architecture with insulator structure202110,205,440Retention flip-flop circuits for low power applications20199,691,764'FinFET cell architecture with power traces'20179,257,429'N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch'20169,076,673'FinFET cell architecture with power traces'20159,048,121'FinFET cell architecture with insulator structure'20158,987,828'N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch'20158,941,150'Power routing in standard cells'20158,924,908'FinFET cell architecture with power traces'20148,742,464'Power routing in standard cells'20148,723,268'N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch'20148,631,374'Cell architecture for increasing transistor size'20148,612,914'Pin routing in standard cells'20138,595,661'N-channel and p-channel finFET cell architecture'20138,561,003'N-channel and P-channel finFET cell architecture with inter-block insulator'20138,513,978'Power routing in standard cell designs'20138,392,862'Structures and methods for optimizing power consumption in an integrated chip design'20138,132,142'Various methods and apparatuses to route multiple power rails to a cell'20127,989,849'Apparatuses and methods for efficient power rail structures for cell libraries'20117,603,634'Various methods and apparatuses to preserve a logic state for a volatile latch circuit'20097,219,324'Various methods and apparatuses to route multiple power rails to a cell'20077,069,522'Various methods and apparatuses to preserve a logic state for a volatile latch circuit'20066,617,621'Gate array architecture using elevated metal levels for customization'20035,943,243'Method and system for removing hardware design overlap'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999Based in Wappingers Falls, NY, US· patent location history
2003–2009Patents assigned to VIRAGE LOGIC CORP (4)· patent assignee history
2003–2021Based in Cupertino, CA, US· patent location history
2011–2021Patents assigned to SYNOPSYS INC (19)· patent assignee history
2012–2014Patents assigned to SHERLEKAR DEEPAK D (6)· patent assignee history
2013–2014Patents assigned to MOROZ VICTOR (3)· patent assignee history
2013Patents assigned to SHERLEKAR DEEPAK (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SYNOPSYS INC | 19 | 2011–2021 |
| SHERLEKAR DEEPAK Dself | 6 | 2012–2014 |
| VIRAGE LOGIC CORP | 4 | 2003–2009 |
| MOROZ VICTOR | 3 | 2013–2014 |
| SHERLEKAR DEEPAKself | 3 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 23 | 2003–2021 |
| Wappingers Falls, New York, US | 1 | 1999 |