Inventor
Satish B. Rao
Inventor
Berkeley, CA, US
Overview
Patents· 13 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication27%
G06FElectric digital data processing15%
B82YSpecific uses or applications of nanostructures8%
C01BNon-metallic elements8%
C25FProcesses for the electrolytic removal of materials from objects8%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light8%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light8%
C30BSingle-crystal growth4%
G02BOptical elements, systems or apparatus4%
G06TImage data processing or generation, in general4%
PatentTitleYear
11,015,263Defect reduction in seeded aluminum nitride crystal growth20219,497,284'Apparatus and method for caching of compressed content in a content delivery network'20168,903,937'Apparatus and method for caching of compressed content in a content delivery network'20148,477,630'Optimal route selection in a content delivery network'20138,194,538'Optimal route selection in a content delivery network'20127,929,429'Optimal route selection in a content delivery network'20117,395,355'Method for caching and delivery of compressed content in a content delivery network'20087,274,658'Optimal route selection in a content delivery network'20077,001,578'Family of discretely sized silicon nanoparticles and method for producing the same'20066,743,406'Family of discretely sized silicon nanoparticles and method for producing the same'20046,078,688'Method for image segmentation by minimizing the ratio between the exterior boundary cost and the cost of the enclosed region'20005,737,233'VLSI circuit layout method based on spreading functions and simulated annealing heuristics to minimize area'19985,465,379'Optical mesh-connected bus interconnect for a computer'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2000Patents assigned to NEC RESEARCH INST INC (3)· patent assignee history
1998Based in Trenton, NJ, US· patent location history
2000Based in Princeton, NJ, US· patent location history
2004–2006Based in Reston, VA, US· patent location history
2007–2016Patents assigned to AKAMAI TECH INC (7)· patent assignee history
2007–2016Based in Berkeley, CA, US· patent location history
2012–2013Patents assigned to BORNSTEIN CLAUDSON F (2)· patent assignee history
2012–2013Patents assigned to CANFIELD TIMOTHY K (2)· patent assignee history
2012–2013Patents assigned to MILLER GARY L (2)· patent assignee history
2021Based in Albany, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AKAMAI TECH INC | 7 | 2007–2016 |
| NEC RESEARCH INST INC | 3 | 1995–2000 |
| BORNSTEIN CLAUDSON F | 2 | 2012–2013 |
| CANFIELD TIMOTHY K | 2 | 2012–2013 |
| MILLER GARY L | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Berkeley, California, US | 7 | 2007–2016 |
| Reston, Virginia, US | 2 | 2004–2006 |
| Albany, New York, US | 1 | 2021 |
| Princeton, New Jersey, US | 1 | 2000 |
| Trenton, New Jersey, US | 1 | 1998 |