LexDanaLexDanabeta
Inventor

Thomas Werner

Inventor
Moritzburg, DE

Overview

61→
Patents
1984–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 61 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H10DInorganic electric semiconductor devices16%
H01LSemiconductor devices8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations2%
G02BOptical elements, systems or apparatus2%
B23QDetails, components, or accessories for machine tools, e.g. arrangements for copying or controlling1%
B24DTools for grinding, buffing or sharpening1%
B28DWorking stone or stone-like materials1%
PatentTitleYear
10,926,431Tool head and glass or glass ceramic article producible using the tool head202110,711,311Genomic rearrangements associated with prostate cancer and methods of using the same202010,370,284Monolithic support for full-surface support of a workpiece201910,014,279Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities20189,822,377'Mutant CD83 promoter and use thereof'20179,627,317'Wafer with improved plating current distribution'20179,455,232'Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure'20169,362,239'Vertical breakdown protection layer'20169,349,641'Wafer with improved plating current distribution'20169,318,468'3-D integrated semiconductor device comprising intermediate heat spreading capabilities'20169,245,860'Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom'20168,835,303'Metallization system of a semiconductor device comprising extra-tapered transition vias'20148,828,887'Restricted stress regions formed in the contact level of a semiconductor device'20148,735,237'Method for increasing penetration depth of drain and source implantation species for a given gate height'20148,716,126'Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions'20148,679,924'Self-aligned multiple gate transistor formed on a bulk substrate'20148,652,341'Method and apparatus for structuring components made of a material composed of silicon oxide'20148,609,524'Method for making semiconductor device comprising replacement gate electrode structures with an enhanced diffusion barrier'20138,482,123'Stress reduction in chip packaging by using a low-temperature chip-package connection regime'20138,420,533'Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding'20138,399,352'Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions'20138,377,820'Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size'20138,368,221'Hybrid contact structure with low aspect ratio contacts in a semiconductor device'20138,357,610'Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics'20138,344,474'Microstructure device including a metallization structure with self-aligned air gaps and refilled air gap exclusion zones'20138,241,973'Method for increasing penetration depth of drain and source implantation species for a given gate height'20128,216,927'Method of reducing contamination by providing a removable polymer protection film during microstructure processing'20128,198,147'Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer'20128,105,962'Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach'20128,080,866'3-D integrated semiconductor device comprising intermediate heat spreading capabilities'20118,048,796'Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material'20118,048,811'Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material'20118,048,736'Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor'20118,040,497'Method and test structure for estimating focus settings in a lithography process based on CD measurements'20118,030,209'Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer'20117,989,352'Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics'20117,977,237'Fabricating vias of different size of a semiconductor device by splitting the via patterning process'20117,955,962'Method of reducing contamination by providing a removable polymer protection film during microstructure processing'20117,951,677'Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition'20117,932,166'Field effect transistor having a stressed contact etch stop layer with reduced conformality'20117,902,581'Semiconductor device comprising a contact structure based on copper and tungsten'20117,871,941'Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device'20117,833,874'Technique for forming an isolation trench as a stress source for strain engineering'20107,800,106'Test structure for OPC-related shorts between lines in a semiconductor device'20107,763,476'Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffraction'20107,764,078'Test structure for monitoring leakage currents in a metallization layer'20107,763,547'Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics'20107,705,352'Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias'20107,622,391'Method of forming an electrically conductive line in an integrated circuit'20097,608,912'Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress'20097,462,563'Method of forming an etch indicator layer for reducing etch non-uniformities'20087,085,300'Integral vertical cavity surface emitting laser and power monitor'20067,030,044'Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric'20067,022,602'Nitrogen-enriched low-k barrier layer for a copper metallization layer'20066,964,874'Void formation monitoring in a damascene process'20056,893,956'Barrier layer for a copper metallization layer including a low-k dielectric'20056,867,610'Test structure for determining the stability of electronic devices comprising connected substrates'20056,724,096'Die corner alignment structure'20046,228,758'Method of making dual damascene conductive interconnections and integrated circuit device comprising same'20015,976,948'Process for forming an isolation region with trench cap'19994,454,495'Layered ultra-thin coherent structures used as electrical resistors having low temperature coefficient of resistivity'1984

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2016Patents assigned to ADVANCED MICRO DEVICES INC (23)· patent assignee history
2001–2016Based in Dresden, DE· patent location history
2008–2018Based in Moritzburg, DE· patent location history
2010–2018Patents assigned to GLOBALFOUNDRIES INC (30)· patent assignee history
2010–2014Based in Reichenberg, DE· patent location history
2011–2017Patents assigned to WERNER THOMAS (20)· patent assignee history
2011–2016Patents assigned to FEUSTEL FRANK (13)· patent assignee history
2012–2016Patents assigned to FROHBERG KAI (11)· patent assignee history
2012–2014Based in Friedewald, DE· patent location history
2019–2021Based in Bingen, DE· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
GLOBALFOUNDRIES INC302010–2018
ADVANCED MICRO DEVICES INC231999–2016
WERNER THOMASself202011–2017
FEUSTEL FRANK132011–2016
FROHBERG KAI112012–2016
Locations
LocationPatentsSpan
Moritzburg, DE302008–2018
Reichenberg, DE122010–2014
Dresden, DE92001–2016
Bingen, DE22019–2021
Friedewald, DE22012–2014