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Inventor

Chandrasekharan Kothandaraman

Inventor
Hopewell Junction, NY, US

Overview

115→
Patents
2002–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 115 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H01LSemiconductor devices14%
H10BElectronic memory devices13%
G11CStatic stores12%
H10NElectric solid-state devices not otherwise provided for12%
H10DInorganic electric semiconductor devices7%
G06FElectric digital data processing4%
G01RMeasuring electric variables3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
H03KPulse technique2%
PatentTitleYear
10,984,948Method of manufacturing inductors in BEOL with particulate magnetic cores202110,957,738Magnetic random access memory (MRAM) structure with small bottom electrode202110,942,072Nanoscale magnetic tunnel junction arrays for sub-micrometer resolution pressure sensor202110,937,828Fabricating embedded magnetoresistive random access memory device with v-shaped magnetic tunnel junction profile202110,840,441Diamond-like carbon hardmask for MRAM202010,784,268OTP elements with high aspect ratio MTJ202010,741,327Inductors in BEOL with particulate magnetic cores202010,741,752Sub-lithographic magnetic tunnel junctions for magnetic random access memory devices202010,727,398MTJ containing device containing a bottom electrode embedded in diamond-like carbon202010,700,263Annealed seed layer for magnetic random access memory202010,644,232Self-aligned and misalignment-tolerant landing pad for magnetoresistive random access memory202010,622,553Cryogenic patterning of magnetic tunnel junctions202010,446,484Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability201910,373,678SRAM margin recovery during burn-in201910,374,152Magnetic tunnel junction based anti-fuses with cascoded transistors201910,361,093Multi time programmable memories using local implantation in high-K/ metal gate technologies201910,355,204Selective growth of seed layer for magneto-resistive random access memory201910,332,591SRAM margin recovery during burn-in201910,211,064Multi time programmable memories using local implantation in high-K/ metal gate technologies201910,203,199Strain monitoring of MRAM arrays201910,168,143Strain monitoring of MRAM arrays201910,170,697Cryogenic patterning of magnetic tunnel junctions201910,170,337Implant after through-silicon via (TSV) etch to getter mobile ions201910,163,493SRAM margin recovery during burn-in201810,142,335Dynamic intrinsic chip identification201810,078,496Magnetic tunnel junction (MTJ) based true random number generators (TRNG)201810,043,584Three terminal fuse structure created by oxygen vacancy traps in hafnium-based oxides201810,008,536Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material201810,002,904Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material20189,953,900Transistor structures gated using a conductor-filled via or trench20189,847,290Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability20179,721,646'Prevention of SRAM burn-in'20179,705,500'Magnetic tunnel junction based chip identification'20179,684,035'Magnetic tunnel junction loaded ring oscillators for MRAM characterization'20179,653,679'Magnetoresistive structures with stressed layer'20179,647,200'Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material'20179,640,228'CMOS device with reading circuit'20179,601,686'Magnetoresistive structures with stressed layer'20179,576,634'Magnetic tunnel junction based chip identification'20179,569,712'Magnetic tunnel junction based chip identification'20179,541,605'Magnetic tunnel junction loaded ring oscillators for MRAM characterization'20179,536,926'Magnetic tunnel junction based anti-fuses with cascoded transistors'20179,495,627'Magnetic tunnel junction based chip identification'20169,476,927'Structure and method to determine through silicon via build integrity'20169,436,845'Physically unclonable fuse using a NOR type memory array'20169,404,953'Structures and methods for monitoring dielectric reliability with through-silicon vias'20169,397,287'Magnetic tunnel junction with post-deposition hydrogenation'20169,298,950'Undiscoverable physical chip identification'20169,208,878'Non-volatile memory based on retention modulation'20159,184,129'Three-terminal antifuse structure having integrated heating elements for a programmable circuit'20159,177,923'Through-substrate via shielding'20159,070,698'Through-substrate via shielding'20159,025,386'Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology'20158,975,910'Through-silicon-via with sacrificial dielectric line'20158,950,008'Undiscoverable physical chip identification'20158,927,427'Anticipatory implant for TSV'20158,907,410'TSV structure with a built-in U-shaped FET transistor for improved characterization'20148,629,049'Electrically programmable fuse using anisometric contacts and fabrication method'20148,629,009'Programmable high-k/metal gate memory device'20148,569,755'Secure anti-fuse with low voltage programming through localized diffusion heating'20138,525,263'Programmable high-k/metal gate memory device'20138,519,507'Electrically programmable fuse using anisometric contacts and fabrication method'20138,415,653'Single mask adder phase change memory element'20138,384,145'Non-volatile memory device using hot-carrier injection'20138,350,264'Secure anti-fuse with low voltage programming through localized diffusion heating'20138,299,570'Efuse containing sige stack'20128,283,202'Single mask adder phase change memory element'20128,278,155'Reprogrammable fuse structure and method'20128,169,321'Radio frequency-enabled electromigration fuse'20128,163,640'Metal gate compatible electrical fuse'20128,159,040'Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor'20128,030,736'Fin anti-fuse with reduced programming voltage'20118,004,059'eFuse containing SiGe stack'20118,004,060'Metal gate compatible electrical antifuse'20117,982,285'Antifuse structure having an integrated heating element'20117,960,809'eFuse with partial SiGe layer and design structure therefor'20117,960,808'Reprogrammable fuse structure and method'20117,943,493'Electrical fuse having a fully silicided fuselink and enhanced flux divergence'20117,880,266'Four-terminal antifuse structure having integrated heating elements for a programmable circuit'20117,838,963'Electrical fuse having a fully silicided fuselink and enhanced flux divergence'20107,825,479'Electrical antifuse having a multi-thickness dielectric layer'20107,750,335'Phase change material structure and related method'20107,745,855'Single crystal fuse on air in bulk silicon'20107,732,893'Electrical fuse structure for higher post-programming resistance'20107,713,792'Fuse structure including monocrystalline semiconductor material layer and gap'20107,714,326'Electrical antifuse with integrated sensor'20107,633,079'Programmable fuse/non-volatile memory structures in BEOL regions using externally heated phase change material'20097,583,125'Methods and apparatus for pulse generation used in characterizing electronic fuses'20097,566,593'Fuse structure including cavity and methods for fabrication thereof'20097,550,323'Electrical fuse with a thinned fuselink middle portion'20097,550,789'Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable'20097,504,875'Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit'20097,485,944'Programmable electronic fuse'20097,442,583'Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable'20087,436,044'Electrical fuses comprising thin film transistors (TFTS), and methods for programming same'20087,391,097'Secure electrically programmable fuse'20087,388,273'Reprogrammable fuse structure and method'20087,354,805'Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology'20087,336,095'Changing chip function based on fuse states'20087,295,057'Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit'20077,270,269'Secure electronic voting device'20077,268,577'Changing chip function based on fuse states'20077,242,072'Electrically programmable fuse for silicon-on-insulator (SOI) technology'20077,227,207'Dense semiconductor fuse array'20077,075,127'Single-poly 2-transistor based fuse element'20067,042,094'Via structure for semiconductor chip'20067,029,955'Optically and electrically programmable silicided polysilicon fuse device'20066,913,954'Programmable fuse device'20056,828,652'Fuse structure for semiconductor device'20046,781,436'Programming transistor in breakdown mode with current compliance'20046,710,640'Active well-bias transistor for programming a fuse'20046,624,499'System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient'20036,617,914'Electrical antifuse with external capacitance'20036,432,760'Method and structure to reduce the damage associated with programming electrical fuses'20026,368,902'Enhanced efuses by the local degradation of the fuse link'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2021Patents assigned to IBM (101)· patent assignee history
2002–2006Patents assigned to INFINEON TECHNOLOGIES AG (10)· patent assignee history
2002–2006Based in Wappingers Falls, NY, US· patent location history
2003–2005Based in Bogota, NJ, US· patent location history
2007–2018Based in Hopewell Junction, NY, US· patent location history
2012–2015Patents assigned to KOTHANDARAMAN CHANDRASEKHARAN (17)· patent assignee history
2012–2014Patents assigned to MOY DAN (5)· patent assignee history
2012–2021Based in New York, NY, US· patent location history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1012002–2021
KOTHANDARAMAN CHANDRASEKHARANself172012–2015
INFINEON TECHNOLOGIES AG102002–2006
GLOBALFOUNDRIES INC62016–2019
MOY DAN52012–2014
Locations
LocationPatentsSpan
Hopewell Junction, New York, US612007–2018
New York, New York, US432012–2021
Wappingers Falls, New York, US62002–2006
Bogota, New Jersey, US52003–2005