Inventor
Darrell S. McGinnis
Inventor
Hillsboro, OR, US
Overview
Patents· 7 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing50%
G11CStatic stores38%
H03MCoding13%
PatentTitleYear
8,612,832'Mechanisms and techniques for providing cache tags in dynamic random access memory'20137,249,274'System and method for scalable clock gearing mechanism'20077,177,989'Retry of a device read transaction'20077,133,960'Logical to physical address mapping of chip selects'20067,127,584'System and method for dynamic rank specific timing adjustments for double data rate (DDR) components'20067,106,633'Write pointer error recovery systems and methods'20066,956,775'Write pointer error recovery'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2013Patents assigned to INTEL CORP (7)· patent assignee history
2005–2007Based in Hillsboro, OR, US· patent location history
2007Based in Sherwood, OR, US· patent location history
2013Patents assigned to AGARWAL RAJAT (1)· patent assignee history
2013Patents assigned to CHINTHAMANI MEENAKSHISUNDARAM R (1)· patent assignee history
2013Patents assigned to HUDDLESTON C SCOTT (1)· patent assignee history
2013Patents assigned to MCGINNIS DARRELL S (1)· patent assignee history
2013Based in Cornelius, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 7 | 2005–2013 |
| AGARWAL RAJAT | 1 | 2013 |
| CHINTHAMANI MEENAKSHISUNDARAM R | 1 | 2013 |
| HUDDLESTON C SCOTT | 1 | 2013 |
| MCGINNIS DARRELL Sself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 5 | 2005–2007 |
| Cornelius, OR, US | 1 | 2013 |
| Sherwood, OR, US | 1 | 2007 |