Inventor
Koichi Motoyama
Inventor
Clifton Park, NY, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1042%
H01LSemiconductor devices35%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10DInorganic electric semiconductor devices6%
C25DProcesses for the electrolytic or electrophoretic production of coatings2%
PatentTitleYear
10,840,325Low resistance metal-insulator-metal capacitor electrode202010,748,812Air-gap containing metal interconnects202010,658,233Dielectric damage-free dual damascene Cu interconnects without barrier at via bottom202010,586,767Hybrid BEOL metallization utilizing selective reflection mask202010,546,815Low resistance interconnect structure with partial seed enhancement liner202010,529,622Void-free metallic interconnect structures with self-formed diffusion barrier layers202010,388,600Binary metallization structure for nanoscale dual damascene interconnects201910,361,119Enlarged contact area structure using noble metal cap and noble metal liner201910,340,355Method of forming a dual metal interconnect structure201910,269,698Binary metallization structure for nanoscale dual damascene interconnects201910,217,664Reflow interconnect using Ru201910,211,101Reflow interconnect using Ru201910,204,828Enabling low resistance gates and contacts integrated with bilayer dielectrics201910,134,674Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects20189,966,305Ion flow barrier structure for interconnect metallization20189,960,078Reflow interconnect using Ru20189,793,213'Ion flow barrier structure for interconnect metallization'20179,780,035'Structure and method for improved stabilization of cobalt cap and/or cobalt liner in interconnects'20179,741,812'Dual metal interconnect structure'20179,418,934'Structure and fabrication method for electromigration immortal nanoscale interconnects'20169,111,938'Copper interconnect with CVD liner and metallic cap'20159,059,176'Copper interconnect with CVD liner and metallic cap'20158,216,940'Method for manufacturing a semiconductor device'20127,892,976'Semiconductor device and method for manufacturing the same'20117,566,975'Semiconductor device and method for manufacturing the same'20096,900,539'Semiconductor device and method for manufacturing the same'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2009Patents assigned to NEC ELECTRONICS CORP (2)· patent assignee history
2005Based in Tokyo, JP· patent location history
2009Based in Kawasaki, JP· patent location history
2011–2015Patents assigned to RENESAS ELECTRONICS CORP (4)· patent assignee history
2011–2012Based in Kanagawa, JP· patent location history
2012–2015Patents assigned to MOTOYAMA KOICHI (2)· patent assignee history
2015–2020Patents assigned to IBM (22)· patent assignee history
2015Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
2015–2020Based in Clifton Park, NY, US· patent location history
2015Based in Albany, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 22 | 2015–2020 |
| RENESAS ELECTRONICS CORP | 4 | 2011–2015 |
| GLOBALFOUNDRIES INC | 2 | 2015 |
| MOTOYAMA KOICHIself | 2 | 2012–2015 |
| NEC ELECTRONICS CORP | 2 | 2005–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Clifton Park, New York, US | 21 | 2015–2020 |
| Kanagawa, JP | 2 | 2011–2012 |
| Albany, New York, US | 1 | 2015 |
| Kawasaki, JP | 1 | 2009 |
| Tokyo, JP | 1 | 2005 |