Inventor

Stefan Rusu

Inventor

Sunnyvale, CA, US

Overview

1992–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 73 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing23%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%

H01LSemiconductor devices10%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

H10DInorganic electric semiconductor devices9%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses5%

H03KPulse technique5%

G01RMeasuring electric variables4%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%

G05FSystems for regulating electric or magnetic variables4%

PatentTitleYear

11,107,931Structure and formation method of semiconductor device structure with nanowires2021 11,094,682Package structure and method of fabricating the same2021 11,031,288Passive components in vias in a stacked integrated circuit package2021 11,025,236Low-power AOI-based flip-flop2021 10,951,201Flip flop standard cell2021 10,930,554Semiconductor device and method for manufacturing the same2021 10,931,264Low-power flip flop circuit2021 10,923,463Method and machine-readable medium for configuring processors with base dies having landing slots2021 10,872,190Method and system for latch-up prevention2020 10,854,499Integrated circuit, system for and method of forming an integrated circuit2020 10,823,921Photonics package integration2020 10,825,797Modular voltage regulators2020 10,560,104Clock synchronization apparatus and method2020 10,522,509Modular voltage regulators2019 10,431,573Method for stacking core and uncore dies having landing slots2019 10,431,696Structure and formation method of semiconductor device structure with nanowire2019 10,403,600Modular voltage regulators2019 10,325,807Semiconductor device and method for manufacturing the same2019 10,326,430Low power flip flop circuit2019 10,269,417Apparatus for adaptive write assist for memory2019 10,236,209Passive components in vias in a stacked integrated circuit package2019 10,128,855Apparatus and method for clock synchronization for inter-die synchronized data transfer2018 10,013,045Apparatus, method, and system for adaptive compensation of reverse temperature dependence2018 10,007,749Converged adaptive compensation scheme2018 9,921,630'Apparatus and method for reducing leakage power of a circuit'2018 9,805,790'Memory cell with retention using resistive memory'2017 9,514,093'Method and apparatus for stacking core and uncore dies having landing slots'2016 9,413,364'Apparatus and method for clock synchronization for inter-die synchronized data transfer'2016 9,385,728'Integrated clock differential buffering'2016 9,342,132'Apparatus, method, and system for adaptive compensation of reverse temperature dependence'2016 9,335,814'Adaptively controlling low power mode operation for a cache memory'2016 9,335,803'Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores'2016 9,207,750'Apparatus and method for reducing leakage power of a circuit'2015 9,087,146'Wear-out equalization techniques for multiple functional units'2015 8,907,737'Apparatus, system and method for configuring signal modulation'2014 8,860,479'Integrated clock differential buffering'2014 7,908,496'Systems and methods for communicating voltage regulation information between a voltage regulator and an integrated circuit'2011 7,669,069'Control of link supply power based on link port mode'2010 7,657,767'Cache leakage shut-off mechanism'2010 7,609,091'Link transmitter with reduced power consumption'2009 7,464,276'Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system in response to compute load'2008 7,281,140'Digital throttle for multiple operating points'2007 7,144,152'Apparatus for thermal management of multiple core microprocessors'2006 7,124,309'Method, system, and apparatus for an efficient power dissipation'2006 7,111,178'Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system'2006 7,069,455'Low power differential link interface methods and apparatuses'2006 7,038,515'Soft-error rate hardened pulsed latch'2006 6,995,552'Voltage modulator circuit to control light emission for non-invasive timing measurements'2006 6,931,559'Multiple mode power throttle mechanism'2005 6,908,227'Apparatus for thermal management of multiple core microprocessors'2005 6,855,946'Fiducial transistor in an integrated circuit'2005 6,788,156'Adaptive variable frequency clock system for high performance low power microprocessors'2004 6,762,629'VCC adaptive dynamically variable frequency clock system for high performance low power microprocessors'2004 6,753,541'Method and apparatus for making and using a beacon fiducial for an integrated circuit'2004 6,707,118'Semiconductor-on-insulator resistor-capacitor circuit'2004 6,608,528'Adaptive variable frequency clock system for high performance low power microprocessors'2003 6,596,980'Method and apparatus to measure statistical variation of electrical signal phase in integrated circuits using time-correlated photon counting'2003 6,524,897'Semiconductor-on-insulator resistor-capacitor circuit'2003 6,519,744'Semiconductor die manufacture method to limit a voltage drop on a power plane thereof by noninvasively measuring voltages on a power plane'2003 6,507,182'Voltage modulator circuit to control light emission for non-invasive timing measurements'2003 6,366,129'Method and apparatus for buffering an input-output node of an integrated circuit'2002 6,201,448'Method and apparatus to reduce clock jitter of an on-chip clock signal'2001 6,092,212'Method and apparatus for driving a strobe signal'2000 6,067,656'Method and apparatus for detecting soft errors in content addressable memory arrays'2000 6,044,417'System for controlling operational characteristics of buffer group where capture registers receive control signals in parallel and update registers transfer control signals to buffer group'2000 5,869,983'Method and apparatus for controlling compensated buffers'1999 5,623,420'Method and apparatus to distribute spare cells within a standard cell region of an integrated circuit'1997 5,598,348'Method and apparatus for analyzing the power network of a VLSI circuit'1997 5,598,035'Integrated circuit package with external storage capacitor for improved signal quality for sensitive integrated circuit elements'1997 5,581,473'Method and apparatus for managing timing requirement specifications and confirmations and generating timing models and constraints for a VLSI circuit'1996 5,307,286'Method for optimizing automatic place and route layout for full scan circuits'1994 5,208,764'Method for optimizing automatic place and route layout for full scan circuits'1993 5,109,168'Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–1997Patents assigned to SUN MICROSYSTEMS INC (7)· patent assignee history

1992–2021Based in Sunnyvale, CA, US· patent location history

1999–2021Patents assigned to INTEL CORP (51)· patent assignee history

2014–2016Patents assigned to RUSU STEFAN (3)· patent assignee history

2014Patents assigned to FAW DONALD L (1)· patent assignee history

2014–2018Based in Santa Clara, CA, US· patent location history

2019–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (15)· patent assignee history

2020Based in Hsinchu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	51	1999–2021
TAIWAN SEMICONDUCTOR MFG CO LTD	15	2019–2021
SUN MICROSYSTEMS INC	7	1992–1997
RUSU STEFANself	3	2014–2016
FAW DONALD L	1	2014

Locations

Location	Patents	Span
Sunnyvale, California, US	65	1992–2021
Santa Clara, California, US	7	2014–2018
Hsinchu, TW	1	2020