Inventor

Sivananda K. Kanakasabapathy

Inventor

Niskayuna, NY, US

Overview

2005–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 188 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices26%

H01LSemiconductor devices24%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%

H10BElectronic memory devices6%

H10NElectric solid-state devices not otherwise provided for3%

G06FElectric digital data processing2%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

G11CStatic stores1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

PatentTitleYear

11,107,821Semiconductor structures with deep trench capacitor and methods of manufacture2021 11,094,824Forming a sacrificial liner for dual channel devices2021 11,081,566Self-aligned contacts for vertical field effect transistors2021 11,075,281Additive core subtractive liner for metal cut etch processes2021 11,056,493Semiconductor structures with deep trench capacitor and methods of manufacture2021 11,018,007Self aligned pattern formation post spacer etchback in tight pitch configurations2021 10,957,583Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs2021 10,957,694Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation2021 10,937,867Conformal doping for punch through stopper in fin field effect transistor devices2021 10,790,393Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning2020 10,741,647Conformal doping for punch through stopper in fin field effect transistor devices2020 10,727,317Bottom contact formation for vertical transistor devices2020 10,707,083High aspect ratio gates2020 10,629,495Low undercut N-P work function metal patterning in nanosheet replacement metal gate process2020 10,622,352Fin cut to prevent replacement gate collapse on STI2020 10,613,438Self-aligned patterning methods which implement directed self-assembly2020 10,615,278Preventing strained fin relaxation2020 10,600,884Additive core subtractive liner for metal cut etch processes2020 10,593,679Static random access memory (SRAM) density scaling by using middle of line (MOL) flow2020 10,593,802Forming a sacrificial liner for dual channel devices2020 10,546,774Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs2020 10,535,662Semiconductor structures including an integrated FinFET with deep trench capacitor and methods of manufacture2020 10,529,569Self aligned pattern formation post spacer etchback in tight pitch configurations2020 10,510,892Forming a sacrificial liner for dual channel devices2019 10,475,886Modified fin cut after epitaxial growth2019 10,453,922Conformal doping for punch through stopper in fin field effect transistor devices2019 10,395,985Self aligned conductive lines with relaxed overlay2019 10,366,928Hybridization fin reveal for uniform fin reveal depth across different fin pitches2019 10,361,207Semiconductor structures with deep trench capacitor and methods of manufacture2019 10,332,971Replacement metal gate stack for diffusion prevention2019 10,326,000FinFET with reduced parasitic capacitance2019 10,312,370Forming a sacrificial liner for dual channel devices2019 10,276,452Low undercut N-P work function metal patterning in nanosheet replacement metal gate process2019 10,269,806Semiconductor structures with deep trench capacitor and methods of manufacture2019 10,249,753Gate cut on a vertical field effect transistor with a defined-width inorganic mask2019 10,249,512Tunable TiOxNy hardmask for multilayer patterning2019 10,249,622Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation2019 10,243,079Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning2019 10,242,981Fin cut during replacement gate formation2019 10,242,952Registration mark formation during sidewall image transfer process2019 10,224,326Fin cut during replacement gate formation2019 10,211,319Stress retention in fins of fin field-effect transistors2019 10,211,321Stress retention in fins of fin field-effect transistors2019 10,170,581FinFET with reduced parasitic capacitance2019 10,170,471Bulk fin formation with vertical fin sidewall profile2019 10,163,721Hybridization fin reveal for uniform fin reveal depth across different fin pitches2018 10,157,745High aspect ratio gates2018 10,134,595High aspect ratio gates2018 10,121,852Structure and process to tuck fin tips self-aligned to gates2018 10,121,661Self aligned pattern formation post spacer etchback in tight pitch configurations2018 10,121,785Pitch scalable active area patterning structure and process for multi-channel fin FET technologies2018 10,121,853Structure and process to tuck fin tips self-aligned to gates2018 10,115,724Double diffusion break gate structure without vestigial antenna capacitance2018 10,083,864Self aligned conductive lines with relaxed overlay2018 10,083,964Double diffusion break gate structure without vestigial antenna capacitance2018 10,079,148Material removal process for self-aligned contacts2018 10,056,290Self-aligned pattern formation for a semiconductor device2018 10,050,039Semiconductor structures with deep trench capacitor and methods of manufacture2018 10,043,760Registration mark formation during sidewall image transfer process2018 10,042,968Semiconductor structures with deep trench capacitor and methods of manufacture2018 10,032,680Strained finFET device fabrication2018 9,997,419Confined eptaxial growth for continued pitch scaling2018 9,991,156Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs2018 9,985,109FinFET with reduced parasitic capacitance2018 9,985,027Stable multiple threshold voltage devices on replacement metal gate CMOS devices2018 9,978,748Method of cutting fins to create diffusion breaks for finFETs2018 9,972,533Aligning conductive vias with trenches2018 9,941,142Tunable TiOxNy hardmask for multilayer patterning2018 9,934,970Self aligned pattern formation post spacer etchback in tight pitch configurations2018 9,935,015Hybridization fin reveal for uniform fin reveal depth across different fin pitches2018 9,929,016'Material removal process for self-aligned contacts'2018 9,917,019'Strained FinFET device fabrication'2018 9,911,647'Self aligned conductive lines'2018 9,905,665'Replacement metal gate stack for diffusion prevention'2018 9,882,048'Gate cut on a vertical field effect transistor with a defined-width inorganic mask'2018 9,881,926'Static random access memory (SRAM) density scaling by using middle of line (MOL) flow'2018 9,881,937'Preventing strained fin relaxation'2018 9,876,074Structure and process to tuck fin tips self-aligned to gates2018 9,859,224'Registration mark formation during sidewall image transfer process'2018 9,852,946Self aligned conductive lines2017 9,842,737'Self-aligned quadruple patterning process'2017 9,805,992'Strained finFET device fabrication'2017 9,805,991'Strained finFET device fabrication'2017 9,799,534'Application of titanium-oxide as a patterning hardmask'2017 9,786,554'Self aligned conductive lines'2017 9,779,944'Method and structure for cut material selection'2017 9,773,893'Forming a sacrificial liner for dual channel devices'2017 9,773,700'Aligning conductive vias with trenches'2017 9,761,455'Material removal process for self-aligned contacts'2017 9,754,798'Hybridization fin reveal for uniform fin reveal depth across different fin pitches'2017 9,741,823'Fin cut during replacement gate formation'2017 9,741,856'Stress retention in fins of fin field-effect transistors'2017 9,728,462'Stable multiple threshold voltage devices on replacement metal gate CMOS devices'2017 9,721,848'Cutting fins and gates in CMOS devices'2017 9,716,184'Enabling large feature alignment marks with sidewall image transfer patterning'2017 9,704,860'Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation'2017 9,673,199'Gate cutting for a vertical transistor device'2017 9,653,573'Replacement metal gate including dielectric gate material'2017 9,640,640'FinFET device with channel strain'2017 9,634,009'System and method for source-drain extension in FinFETs'2017 9,627,510'Structure and method for replacement gate integration with self-aligned contacts'2017 9,607,886'Self aligned conductive lines with relaxed overlay'2017 9,589,958'Pitch scalable active area patterning structure and process for multi-channel finFET technologies'2017 9,589,850'Method for controlled recessing of materials in cavities in IC devices'2017 9,589,845'Fin cut enabling single diffusion breaks'2017 9,583,563'Conformal doping for punch through stopper in fin field effect transistor devices'2017 9,576,979'Preventing strained fin relaxation by sealing fin ends'2017 9,576,096'Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture'2017 9,564,438'Semiconductor structure containing semiconductor fins and insulating fence fins on a same substrate'2017 9,548,379'Asymmetric multi-gate FinFET'2017 9,543,435'Asymmetric multi-gate finFET'2017 9,536,744'Enabling large feature alignment marks with sidewall image transfer patterning'2017 9,536,791'Stable multiple threshold voltage devices on replacement metal gate CMOS devices'2017 9,515,089'Bulk fin formation with vertical fin sidewall profile'2016 9,515,141'FinFET device with channel strain'2016 9,502,411'Strained finFET device fabrication'2016 9,472,447'Confined eptaxial growth for continued pitch scaling'2016 9,472,506'Registration mark formation during sidewall image transfer process'2016 9,472,415'Directional chemical oxide etch technique'2016 9,431,399'Method for forming merged contact for semiconductor device'2016 9,331,148'FinFET device with channel strain'2016 9,312,136'Replacement metal gate stack for diffusion prevention'2016 9,305,845'Self-aligned quadruple patterning process'2016 9,299,705'Method of forming semiconductor fins and insulating fence fins on a same substrate'2016 9,287,135'Sidewall image transfer process for fin patterning'2016 9,209,178'finFET isolation by selective cyclic etch'2015 9,064,744'Structure and method to realize conformal doping in deep trench applications'2015 9,064,813'Trench patterning with block first sidewall image transfer'2015 8,987,800'Semiconductor structures with deep trench capacitor and methods of manufacture'2015 8,946,802'Method of eDRAM DT strap formation in FinFET device structure'2015 8,927,365'Method of eDRAM DT strap formation in FinFET device structure'2015 8,906,793'Borderless contact for an aluminum-containing gate'2014 8,901,670'Semiconductor device including multiple metal semiconductor alloy region and a gate structure covered by a continuous encapsulating layer'2014 8,901,667'High performance non-planar semiconductor devices with metal filled inter-fin gaps'2014 8,890,255'Structure and method for stress latching in non-planar semiconductor devices'2014 8,847,338'Method for forming a self-aligned hard mask for contact to a tunnel junction'2014 8,835,232'Low external resistance ETSOI transistors'2014 8,802,565'Semiconductor plural gate lengths'2014 8,779,515'Semiconductor structure containing an aluminum-containing replacement gate electrode'2014 8,753,934'Structure and method to integrate embedded DRAM with FinFET'2014 8,741,752'Borderless contacts in semiconductor devices'2014 8,735,296'Method of simultaneously forming multiple structures having different critical dimensions using sidewall transfer'2014 8,673,165'Sidewall image transfer process with multiple critical dimensions'2014 8,653,610'High performance non-planar semiconductor devices with metal filled inter-fin gaps'2014 8,637,384'FinFET parasitic capacitance reduction using air gap'2014 8,637,930'FinFET parasitic capacitance reduction using air gap'2014 8,637,406'Image transfer process employing a hard mask layer'2014 8,637,908'Borderless contacts in semiconductor devices'2014 8,614,486'Low resistance source and drain extensions for ETSOI'2013 8,586,478'Method of making a semiconductor device'2013 8,586,482'Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation'2013 8,580,692'Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation'2013 8,563,225'Forming a self-aligned hard mask for contact to a tunnel junction'2013 8,541,275'Single metal gate CMOS integration by intermixing polarity specific capping layers'2013 8,518,824'Self aligning via patterning'2013 8,492,270'Structure for nano-scale metallization and method for fabricating same'2013 8,486,778'Low resistance source and drain extensions for ETSOI'2013 8,455,364'Sidewall image transfer using the lithographic stack as the mandrel'2013 8,421,139'Structure and method to integrate embedded DRAM with finfet'2013 8,420,464'Spacer as hard mask scheme for in-situ doping in CMOS finFETs'2013 8,394,684'Structure and method for stress latching in non-planar semiconductor devices'2013 8,377,795'Cut first methodology for double exposure double etch integration'2013 8,358,012'Metal semiconductor alloy structure for low contact resistance'2013 8,298,943'Self aligning via patterning'2012 8,164,128'Magnetic devices and techniques for formation thereof'2012 8,133,746'Method for semiconductor gate hardmask removal and decoupling of implants'2012 8,124,525'Method of forming self-aligned local interconnect and structure formed thereby'2012 8,120,946'Stacked magnetic devices'2012 7,943,458'Methods for obtaining gate stacks with tunable threshold voltage and scaling'2011 7,935,637'Resist stripping methods using backfilling material layer'2011 7,919,379'Dielectric spacer removal'2011 7,825,000'Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions'2010 7,803,639'Method of forming vertical contacts in integrated circuits'2010 7,782,660'Magnetically de-coupling magnetic memory cells and bit/word lines for reducing bit selection errors'2010 7,772,663'Method and apparatus for bitline and contact via integration in magnetic random access memory arrays'2010 7,723,813'Method and structure for improved alignment in MRAM integration'2010 7,642,147'Methods for removing sidewall spacers'2010 7,550,044'Hard mask structure for patterning of materials'2009 7,531,367'Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit'2009 7,507,633'Method and structure for improved alignment in MRAM integration'2009 7,442,647'Structure and method for formation of cladded interconnects for MRAMs'2008 7,399,646'Magnetic devices and techniques for formation thereof'2008 7,381,343'Hard mask structure for patterning of materials'2008 7,374,952'Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof'2008 7,112,861'Magnetic tunnel junction cap structure and method for forming the same'2006 7,033,881'Method for fabricating magnetic field concentrators as liners around conductive wires in microelectronic devices'2006 6,933,204'Method for improved alignment of magnetic tunnel junction elements'2005 6,875,700'Ion-Ion plasma processing with bias modulation synchronized to time-modulated discharges'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2021Patents assigned to IBM (182)· patent assignee history

2005–2012Based in Hopewell Junction, NY, US· patent location history

2008–2021Based in Niskayuna, NY, US· patent location history

2011–2018Based in Albany, NY, US· patent location history

2012–2014Patents assigned to KANAKASABAPATHY SIVANANDA K (26)· patent assignee history

2012–2015Patents assigned to JAGANNATHAN HEMANTH (12)· patent assignee history

2012–2015Patents assigned to KANAKASABAPATHY SIVANANDA (11)· patent assignee history

2012–2014Patents assigned to YIN YUNPENG (6)· patent assignee history

2017Based in Schenectady, NY, US· patent location history

2019–2021Based in Pleasanton, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	182	2005–2021
KANAKASABAPATHY SIVANANDA Kself	26	2012–2014
JAGANNATHAN HEMANTH	12	2012–2015
KANAKASABAPATHY SIVANANDAself	11	2012–2015
YIN YUNPENG	6	2012–2014

Locations

Location	Patents	Span
Niskayuna, New York, US	149	2008–2021
Hopewell Junction, New York, US	15	2005–2012
Pleasanton, California, US	12	2019–2021
Albany, New York, US	9	2011–2018
Schenectady, New York, US	1	2017