Inventor

R. Scott List

Inventor

Beaverton, OR, US

Overview

1998–2011

Patent span

Electricity

Primary field (CPC H)

Patents· 57 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1045%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%

H10DInorganic electric semiconductor devices15%

F04BPositive-displacement machines for liquids6%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

B81BMicrostructural devices or systems, e.g. micromechanical devices2%

B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%

B82YSpecific uses or applications of nanostructures2%

H10NElectric solid-state devices not otherwise provided for2%

A47LDomestic washing or cleaning1%

PatentTitleYear

7,960,226'Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness'2011 7,893,481'Top electrode barrier for on-chip die de-coupling capacitor and method of making same'2011 7,843,036'Enhanced on-chip decoupling capacitors and method of making same'2010 7,842,553'Cooling micro-channels'2010 7,723,208'Integrated re-combiner for electroosmotic pumps using porous frits'2010 7,696,015'Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips'2010 7,667,319'Electroosmotic pump using nanoporous dielectric frit'2010 7,615,462'Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack'2009 7,576,432'Using external radiators with electroosmotic pumps for cooling integrated circuits'2009 7,569,426'Apparatus and method integrating an electro-osmotic pump and microchannel assembly into a die package'2009 7,537,954'Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same'2009 7,416,954'Enhanced on-chip decoupling capacitors and method of making same'2008 7,355,277'Apparatus and method integrating an electro-osmotic pump and microchannel assembly into a die package'2008 7,348,217'Method and structure for interfacing electronic devices'2008 7,300,871'Method of doping a conductive layer near a via'2007 7,274,106'Packaged electroosmotic pumps using porous frits for cooling integrated circuits'2007 7,256,089'Top electrode barrier for on-chip die de-coupling capacitor and method of making same'2007 7,227,257'Cooling micro-channels'2007 7,157,787'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices'2007 7,148,565'Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack'2006 7,138,678'Enhanced on-chip decoupling capacitors and method of making same'2006 7,129,172'Bonded wafer processing method'2006 7,120,817'Method of signal distribution based on a standing wave within a closed loop path'2006 7,105,382'Self-aligned electrodes contained within the trenches of an electroosmotic pump'2006 7,084,495'Electroosmotic pumps using porous frits for cooling integrated circuit stacks'2006 7,056,813'Methods of forming backside connections on a wafer stack'2006 7,056,807'Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack'2006 7,037,804'Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration'2006 7,034,394'Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same'2006 7,033,882'Method of forming on-chip decoupling capacitor by selectively etching grain boundaries in electrode'2006 6,992,381'Using external radiators with electroosmotic pumps for cooling integrated circuits'2006 6,981,849'Electro-osmotic pumps and micro-channels'2006 6,977,435'Thick metal layer integrated process flow to improve power delivery and mechanical buffering'2005 6,975,016'Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof'2005 6,908,565'Etch thinning techniques for wafer-to-wafer vertical stacks'2005 6,897,125'Methods of forming backside connections on a wafer stack'2005 6,887,769'Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same'2005 6,888,716'On-die de-coupling capacitor using bumps or bars'2005 6,870,270'Method and structure for interfacing electronic devices'2005 6,861,274'Method of making a SDI electroosmotic pump using nanoporous dielectric frit'2005 6,833,321'Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability'2004 6,800,928'Porous integrated circuit dielectric with decreased surface porosity'2004 6,790,748'Thinning techniques for wafer-to-wafer vertical stacks'2004 6,790,780'Fabrication of 3-D capacitor with dual damascene process'2004 6,784,121'Integrated circuit dielectric and method'2004 6,762,076'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices'2004 6,737,728'On-chip decoupling capacitor and method of making same'2004 6,737,699'Enhanced on-chip decoupling capacitors and method of making same'2004 6,706,584'On-die de-coupling capacitor using bumps or bars and method of making same'2004 6,664,168'Method of making an on-die decoupling capacitor for a semiconductor device'2003 6,661,085'Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack'2003 6,645,832'Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack'2003 6,204,200'Process scheme to form controlled airgaps between interconnect lines to reduce capacitance'2001 6,127,203'Thermoplastic mounting of a semiconductor die to a substrate having a mismatched coefficient of thermal expansion'2000 6,059,553'Integrated circuit dielectrics'2000 5,959,340'Thermoplastic mounting of a semiconductor die to a substrate having a mismatched coefficient of thermal expansion'1999 5,850,657'Woodworking tool for preparing a wood surface for finishing'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998Patents assigned to HYDE TOOLS (1)· patent assignee history

1998Based in Northborough, MA, US· patent location history

1999–2000Patents assigned to DRS TECHNOLOGIES INC (2)· patent assignee history

1999–2004Based in Dallas, TX, US· patent location history

2000–2004Patents assigned to TEXAS INSTRUMENTS INC (4)· patent assignee history

2003–2011Patents assigned to INTEL CORP (50)· patent assignee history

2003–2011Based in Beaverton, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	50	2003–2011
TEXAS INSTRUMENTS INC	4	2000–2004
DRS TECHNOLOGIES INC	2	1999–2000
HYDE TOOLS	1	1998

Locations

Location	Patents	Span
Beaverton, OR, US	51	2003–2011
Dallas, Texas, US	5	1999–2004
Northborough, Massachusetts, US	1	1998