Inventor

Kazunori Imaoka

Inventor

Komae, JP

Overview

1986–2001

Patent span

Electricity

Primary field (CPC H)

Patents· 16 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%

H10DInorganic electric semiconductor devices21%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%

H10BElectronic memory devices5%

B24BMachines, devices, or processes for grinding or polishing3%

G11CStatic stores3%

PatentTitleYear

6,232,663'Semiconductor device having interlayer insulator and method for fabricating thereof'2001 5,498,893'Semiconductor device having SOI substrate and fabrication method thereof'1996 5,426,073'Method of fabricating semiconductor devices using an intermediate grinding step'1995 5,250,836'Semiconductor device having silicon-on-insulator structure'1993 5,238,857'Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure'1993 5,231,045'Method of producing semiconductor-on-insulator structure by besol process with charged insulating layers'1993 5,162,254'Semiconductor device having a SOI substrate and fabrication method thereof'1992 5,148,247'Semiconductor device having trench isolation'1992 5,094,963'Process for producing a semiconductor device with a bulk-defect region having a nonuniform depth'1992 5,075,249'Method of making a BIC memory cell having contact openings with straight sidewalls and sharp-edge rims'1991 5,066,993'Semiconductor device having semiconductor-on-insulator structure'1991 5,017,998'Semiconductor device using SOI substrate'1991 4,970,568'Semiconductor device and a process for producing a semiconductor device'1990 4,918,499'Semiconductor device with improved isolation between trench capacitors'1990 4,801,559'Process for forming planar wiring using polysilicon to fill gaps'1989 4,597,804'Methods of forming denuded zone in wafer by intrinsic gettering and forming bipolar transistor therein'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–2001Patents assigned to FUJITSU LTD (16)· patent assignee history

1986–1996Based in Komae, JP· patent location history

1993Based in Tokyo, JP· patent location history

2001Patents assigned to ADVANCED MICRO DEVICES INC (1)· patent assignee history

2001Patents assigned to FUJITSU AMD SEMICONDUCTOR LTD (1)· patent assignee history

2001Based in Aizuwakamatsu, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
FUJITSU LTD	16	1986–2001
ADVANCED MICRO DEVICES INC	1	2001
FUJITSU AMD SEMICONDUCTOR LTD	1	2001

Locations

Location	Patents	Span
Komae, JP	14	1986–1996
Aizuwakamatsu, JP	1	2001
Tokyo, JP	1	1993