Inventor

ADARSH RAJASHEKHAR

Inventor
US

Overview

46→
Patents
2021–2026
Patent span
Electricity
Primary field (CPC H)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices31%
H01LSemiconductor devices26%
H10DInorganic electric semiconductor devices16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
G11CStatic stores4%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
12,581,652Three-dimensional memory devices having channel cap structures and methods for forming the same202612,575,100Three-dimensional memory device including discrete charge storage elements and method of making thereof202612,484,222Three-dimensional memory device and method of making thereof by non-conformal selective deposition of insulating spacers in a memory opening202512,457,738Three-dimensional memory device containing engineered charge storage elements and methods for forming the same202512,453,088Three-dimensional memory device including discrete charge storage elements and methods of forming the same202512,432,917Three-dimensional memory device including discrete memory elements and method of making the same202512,387,976Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202512,363,905Memory device containing composition-controlled ferroelectric memory elements and method of making the same202512,362,301Bonded memory devices and methods of making the same202512,342,537Three-dimensional memory device containing epitaxial pedestals and top source contact202512,317,502Three-dimensional memory device containing ferroelectric-assisted memory elements and method of making the same202512,289,889Three-dimensional memory device containing templated crystalline ferroelectric memory elements and method of making thereof202512,261,080Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202512,255,242Three-dimensional memory device including vertical stack of tubular graded silicon oxynitride portions202512,243,776Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings202512,219,776Ferroelectric devices including a single crystalline ferroelectric layer and method of making the same202512,137,554Three-dimensional memory device with word-line etch stop liners and method of making thereof202412,137,565Three-dimensional memory device with vertical word line barrier and methods for forming the same202412,096,636Semiconductor device containing bit lines separated by air gaps and methods for forming the same202412,035,535Three-dimensional NOR array including vertical word lines and discrete memory elements and methods of manufacture202411,996,462Ferroelectric field effect transistors having enhanced memory window and methods of making the same202411,984,395Semiconductor device containing bit lines separated by air gaps and methods for forming the same202411,973,123Ferroelectric devices including a single crystalline ferroelectric layer and method of making the same202411,948,902Bonded assembly including an airgap containing bonding-level dielectric layer and methods of forming the same202411,877,446Three-dimensional memory device with electrically conductive layers containing vertical tubular liners and methods for forming the same202411,631,695Three-dimensional memory device containing composite word lines containing metal and silicide and method of making thereof202311,594,553Three-dimensional ferroelectric memory device containing lattice-matched templates and methods of making the same202311,569,260Three-dimensional memory device including discrete memory elements and method of making the same202311,545,506Ferroelectric field effect transistors having enhanced memory window and methods of making the same202311,527,500Semiconductor structure containing multilayer bonding pads and methods of forming the same202211,521,984Three-dimensional memory device containing low resistance source-level contact and method of making thereof202211,482,539Three-dimensional memory device including metal silicide source regions and methods for forming the same202211,450,687Multibit ferroelectric memory cells and methods for forming the same202211,437,270Three-dimensional memory device containing word lines formed by selective tungsten growth on nucleation controlling surfaces and methods of manufacturing the same202211,424,231Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same202211,424,265Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same202211,309,332Three-dimensional memory device containing ferroelectric memory elements encapsulated by transition metal-containing conductive elements and method of making thereof202211,309,301Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same202211,302,716Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same202211,282,848Three-dimensional memory device including ferroelectric-metal-insulator memory cells and methods of making the same202211,239,254Three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same202211,239,253Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same202211,217,532Three-dimensional memory device containing compositionally graded word line diffusion barrier layer for and methods of forming the same202211,201,139Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same202111,177,280Three-dimensional memory device including wrap around word lines and methods of forming the same202111,145,628Semiconductor structure containing reentrant shaped bonding pads and methods of forming the same2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to SANDISK TECHNOLOGIES LLC (46)· patent assignee history
2021–2026Based in US· patent location history
2025–2026Patents assigned to SANDISK TECHNOLOGIES INC (15)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK TECHNOLOGIES LLC462021–2026
SANDISK TECHNOLOGIES INC152025–2026
Locations
LocationPatentsSpan
US462021–2026