Inventor
Uygar E. Avci
Inventor
Portland, OR, US
Overview
Patents· 56 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices25%
H10DInorganic electric semiconductor devices22%
H10BElectronic memory devices14%
G11CStatic stores7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
H03KPulse technique5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
G06FElectric digital data processing3%
B82YSpecific uses or applications of nanostructures3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
PatentTitleYear
11,107,908Transistors with metal source and drain contacts including a Heusler alloy202111,063,131Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineering202111,056,593Semiconductor devices with metal contacts including crystalline alloys202111,004,868Memory field-effect transistors and methods of manufacturing the same202110,998,339One transistor and ferroelectric FET based memory cell202110,944,399Multi-level spin logic202110,916,547Floating body memory cell having gates favoring different conductivity type regions202110,910,556Magnetic and spin logic devices based on Jahn-Teller materials202110,901,486Configurable interconnect apparatus and method202110,886,265Integrated circuit device with a two-dimensional semiconductor material and a dielectric material that includes fixed charges202110,886,286Vertical memory control circuitry located in interconnect layers202110,861,861Memory including a perovskite material202010,832,761Polarization gate stack SRAM202010,777,250Save-restore circuitry with metal-ferroelectric-metal devices202010,734,378Transistor threshold voltage variation optimization202010,720,434Floating body memory cell having gates favoring different conductivity type regions202010,720,504Transistor with dynamic threshold voltage for low-leakage standby and high speed active mode202010,720,438Memory array with ferroelectric elements202010,707,846Tunnel field-effect transistor (TFET) based high-density and low-power sequential202010,651,182Three-dimensional ferroelectric NOR-type memory202010,573,385Ferroelectric based memory cell with non-volatile retention202010,559,349Polarization gate stack SRAM202010,553,694Transistors with temperature compensating gate structures202010,535,770Scaled TFET transistor formed using nanowire with surface termination202010,522,683Transistors with ballistic or quasi-ballistic carrier behavior and low resistance in source and drain nodes201910,468,489Isolation structures for an integrated circuit element and method of making same201910,381,350Floating body memory cell having gates favoring different conductivity type regions201910,355,005Semi-volatile embedded memory with between-fin floating-gate device and method201910,261,923Configurable interconnect apparatus and method201910,236,345Field effect transistor having a Fermi filter between a source and source contact thereof201910,186,582Graphene fluorination for integration of graphene with insulators and devices201910,128,356P-tunneling field effect transistor device with pocket201810,121,792Floating body memory cell having gates favoring different conductivity type regions20189,997,227Non-volatile ferroelectric logic with granular power-gating20189,985,611Tunnel field-effect transistor (TFET) based high-density and low-power sequential20189,952,823Architecture for seamless integrated display system20189,911,835'Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs'20189,871,106'Heterogeneous pocket for tunneling field effect transistors (TFETs)'20189,842,643'Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors'20179,786,667'Floating body memory cell having gates favoring different conductivity type regions'20179,741,832'Tunneling field effect transistors with a variable bandgap channel'20179,646,970'Floating body memory cell having gates favoring different conductivity type regions'20179,583,566'Reduced scale resonant tunneling field effect transistor'20179,583,602'Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs'20179,520,399'Floating body memory cell having gates favoring different conductivity type regions'20169,490,780'Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors'20169,418,997'Floating body memory cell having gates favoring different conductivity type regions'20169,412,872'N-type and P-type tunneling field effect transistors (TFETs)'20169,361,059'Architecture for seamless integrated display system'20169,275,999'Floating body memory cell having gates favoring different conductivity type regions'20169,209,288'Reduced scale resonant tunneling field effect transistor'20158,980,707'Floating body memory cell having gates favoring different conductivity type regions'20158,890,120'Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs'20148,569,812'Floating body memory cell having gates favoring different conductivity type regions'20138,217,435'Floating body memory cell having gates favoring different conductivity type regions'20127,652,910'Floating body memory array'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2021Patents assigned to INTEL CORP (56)· patent assignee history
2010–2013Based in Beaverton, OR, US· patent location history
2012–2017Patents assigned to AVCI UYGAR E (8)· patent assignee history
2012–2017Patents assigned to BAN IBRAHIM (6)· patent assignee history
2012–2017Patents assigned to CHANG PETER L D (6)· patent assignee history
2014–2021Based in Portland, OR, US· patent location history
2015–2017Patents assigned to KENCKE DAVID (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 56 | 2010–2021 |
| AVCI UYGAR Eself | 8 | 2012–2017 |
| BAN IBRAHIM | 6 | 2012–2017 |
| CHANG PETER L D | 6 | 2012–2017 |
| KENCKE DAVID | 4 | 2015–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 53 | 2014–2021 |
| Beaverton, OR, US | 3 | 2010–2013 |