Inventor
Juergen Boemmels
Inventor
Heverlee, BE
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H01LSemiconductor devices23%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10DInorganic electric semiconductor devices17%
B82YSpecific uses or applications of nanostructures2%
H10BElectronic memory devices2%
PatentTitleYear
11,127,627Method for forming an interconnection structure202110,847,415Self-aligned gate contact202010,833,161Semiconductor device and method202010,763,159Method for forming a multi-level interconnect structure202010,748,815Three-dimensional semiconductor device and method of manufacturing same202010,566,236Method of forming vertical channel devices202010,546,930Method of forming vertical channel devices202010,395,978Method of patterning target layer201910,374,084Vertical channel devices and method of fabricating same201910,242,907Method for interrupting a line in an interconnect20199,859,161'Self-aligned interconnects'20188,741,770'Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process'20148,658,494'Dual contact metallization including electroless plating in a semiconductor device'20148,404,577'Semiconductor device having a grain orientation layer'20138,198,190'Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process'20128,097,536'Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layer'20128,048,811'Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material'20118,039,398'Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices'20117,781,329'Reducing leakage in dielectric materials including metal regions including a metal cap layer in semiconductor devices'20107,767,593'Semiconductor device including field effect transistors laterally enclosed by interlayer dielectric material having increased intrinsic stress'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2012Patents assigned to ADVANCED MICRO DEVICES INC (4)· patent assignee history
2010–2014Based in Dresden, DE· patent location history
2011–2020Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history
2012–2014Patents assigned to BOEMMELS JUERGEN (5)· patent assignee history
2012–2014Patents assigned to RICHTER RALF (3)· patent assignee history
2018–2021Patents assigned to IMEC VZW (11)· patent assignee history
2018–2021Based in Heverlee, BE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IMEC VZW | 11 | 2018–2021 |
| GLOBALFOUNDRIES INC | 6 | 2011–2020 |
| BOEMMELS JUERGENself | 5 | 2012–2014 |
| ADVANCED MICRO DEVICES INC | 4 | 2010–2012 |
| RICHTER RALF | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Heverlee, BE | 11 | 2018–2021 |
| Dresden, DE | 9 | 2010–2014 |