Inventor
Tse-Liang Ying
Inventor
Hsinchu, TW
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H10BElectronic memory devices25%
H10DInorganic electric semiconductor devices13%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
H01FMagnets8%
H10HInorganic light-emitting semiconductor devices having potential barriers8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
E04BGeneral building constructions3%
PatentTitleYear
RE043426'Fabrication method of transparent electrode on visible light-emitting diode'20127,541,205'Fabrication method of transparent electrode on visible light-emitting diode'20097,192,794'Fabrication method of transparent electrode on visible light-emitting diode'20076,436,762'Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins'20026,433,665'High efficiency thin film inductor'20026,373,369'High efficiency thin film inductor'20026,307,213'Method for making a fuse structure for improved repaired yields on semiconductor memory devices'20016,306,767'Self-aligned etching method for forming high areal density patterned microelectronic structures'20016,287,939'Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation'20016,278,352'High efficiency thin film inductor'20016,258,662'Method for forming cylindrical DRAM capacitors'20016,214,715'Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition'20016,207,492'Common gate and salicide word line process for low cost embedded DRAM devices'20016,194,234'Method to evaluate hemisperical grain (HSG) polysilicon surface'20016,187,659'Node process integration technology to improve data retention for logic based embedded dram'20016,174,802'Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition'20016,168,984'Reduction of the aspect ratio of deep contact holes for embedded DRAM devices'20016,162,686'Method for forming a fuse in integrated circuit application'20006,121,073'Method for making a fuse structure for improved repaired yields on semiconductor memory devices'20006,093,619'Method to form trench-free buried contact in process with STI technology'20006,080,637'Shallow trench isolation technology to eliminate a kink effect'20006,037,222'Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology'20005,946,596'Method for preventing polycide line deformation by polycide hardening'19995,922,515'Approaches to integrate the deep contact module'19995,885,865'Method for making low-topography buried capacitor by a two stage etching process and device made'19995,811,331'Formation of a stacked cylindrical capacitor module in the DRAM technology'19985,753,547'Formation of a cylindrical polysilicon module in dram technology'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2002Patents assigned to TAIWAN SEMICONDUCTOR MFG (22)· patent assignee history
1998–2002Based in Hsinchu, TW· patent location history
2002Patents assigned to TAIWAN SEMICONDUCTOR MANUFACTO (1)· patent assignee history
2002–2012Based in Tainan, TW· patent location history
2007Patents assigned to EPITECH TECHNOLOGY CORP (1)· patent assignee history
2009–2012Patents assigned to EPISTAR CORP (2)· patent assignee history
2012Patents assigned to CHEN SHI-MING (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 22 | 1998–2002 |
| EPISTAR CORP | 2 | 2009–2012 |
| CHEN SHI-MING | 1 | 2012 |
| EPITECH TECHNOLOGY CORP | 1 | 2007 |
| TAIWAN SEMICONDUCTOR MANUFACTO | 1 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 23 | 1998–2002 |
| Tainan, TW | 4 | 2002–2012 |