Inventor
Chih-Ta Wu
Inventor
Hsinchu, TW
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices23%
H10BElectronic memory devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
C23CCoating metallic material6%
H01LSemiconductor devices6%
H10NElectric solid-state devices not otherwise provided for6%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
LOC143%
PatentTitleYear
9,418,999'MIM capacitors with improved reliability'20168,889,507'MIM capacitors with improved reliability'20147,851,324'Method of forming metal-insulator-metal structure'20107,786,552'Semiconductor device having hydrogen-containing layer'20107,622,347'Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor'20097,554,145'Magnetic memory cells and manufacturing methods'20097,443,005'Lens structures suitable for use in image sensors and method for making the same'20087,202,130'Spacer for a split gate flash memory cell and a memory cell employing the same'20077,199,001'Method of forming MIM capacitor electrodes'20077,180,116'Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor'20077,172,908'Magnetic memory cells and manufacturing methods'20077,169,713'Atomic layer deposition (ALD) method with enhanced deposition rate'20076,803,291'Method to preserve alignment mark optical integrity'20046,777,336'Method of forming a shallow trench isolation structure'2004D0465485'Personal digital ticketing processor'20026,265,269'Method for fabricating a concave bottom oxide in a trench'20016,265,233'Method for determining crack limit of film deposited on semiconductor wafer'20016,242,365'Method for preventing film deposited on semiconductor wafer from cracking'20016,150,238'Method for fabricating a trench isolation'20006,090,725'Method for preventing bubble defects in BPSG film'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2001Patents assigned to MOSEL VITELIC INC (5)· patent assignee history
2000–2016Based in Hsinchu, TW· patent location history
2002Based in Taipei, TW· patent location history
2004–2014Patents assigned to TAIWAN SEMICONDUCTOR MFG (12)· patent assignee history
2014Patents assigned to CHANG LUCY (1)· patent assignee history
2014Patents assigned to CHEN CHIA-LIN (1)· patent assignee history
2014Patents assigned to HSU CHERN-YOW (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 12 | 2004–2014 |
| MOSEL VITELIC INC | 5 | 2000–2001 |
| CHANG LUCY | 1 | 2014 |
| CHEN CHIA-LIN | 1 | 2014 |
| HSU CHERN-YOW | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 19 | 2000–2016 |
| Taipei, TW | 1 | 2002 |