Inventor
RAMAMOORTHY RAMESH
Inventor
US
Overview
Patents· 53 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices23%
H01LSemiconductor devices20%
H10BElectronic memory devices14%
H03KPulse technique12%
G11CStatic stores9%
G06FElectric digital data processing6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G06NComputing arrangements based on specific computational models2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
12,476,640Perovskite-based magnetoelectric spin-orbit logic devices202512,457,752High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor202512,308,837Multiplier with non-linear polar material202512,272,675Method of forming 3D stacked compute and memory with copper pillars202512,262,543High density ferroelectric random access memory (FeRAM) devices and methods of fabrication202512,223,992High-density low voltage ferroelectric differential memory bit-cell with shared plate- line202512,200,941Pillar capacitor and method of fabricating such202512,137,574Integration of ferroelectric memory devices having stacked electrodes with transistors202412,126,339Apparatus with selectable majority gate and combinational logic gate outputs202412,113,097Ferroelectric capacitor integrated with logic202412,107,579Method for conditioning majority or minority gate202412,094,923Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based memory devices202412,088,297Majority gate based low power ferroelectric based adder with reset mechanism202411,908,704Method of fabricating a perovskite-material based planar capacitor using rapid thermal annealing (RTA) methodologies202411,894,417Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies202411,863,183Low power non-linear polar material based threshold logic gate multiplier202411,832,451High density ferroelectric random access memory (FeRAM) devices and methods of fabrication202311,769,790Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based trench capacitors202311,764,790Majority logic gate having paraelectric input capacitors coupled to a conditioning scheme202311,764,1903D stacked compute and memory with copper pillars202311,758,738Integration of ferroelectric memory devices with transistors202311,744,081Ferroelectric device film stacks with texturing layer which is part of a bottom electrode, and method of forming such202311,742,860Fabrication of a majority logic gate having non-linear input capacitors202311,716,858Ferroelectric device film stacks with texturing layer which is part of a bottom electrode and a barrier, and method of forming such202311,711,083Majority gate based low power ferroelectric based adder with reset mechanism202311,705,906Majority logic gate having ferroelectric input capacitors and a pulsing scheme coupled to a conditioning logic202311,659,714Ferroelectric device film stacks with texturing layer, and method of forming such202311,641,747Integration of a ferroelectric memory device with a transistor202311,637,090Method of forming a 3D stacked compute and memory202311,616,507Ferroelectric based latch202311,539,368Majority logic gate with input paraelectric capacitors202211,522,044Ferroelectric capacitor integrated with logic202211,521,9533D stacked ferroelectric compute and memory202211,502,691Method for using and forming low power ferroelectric based majority logic gate adder202211,482,528Pillar capacitor and method of fabricating such202211,482,529High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor202211,476,260High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor202211,476,261High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor202211,451,232Majority logic gate based flip-flop with non-linear polar material202211,430,861Ferroelectric capacitor and method of patterning such202211,418,197Majority logic gate having paraelectric input capacitors and a local conditioning mechanism202211,394,3872-input NAND gate with non-linear input capacitors202211,381,244Low power ferroelectric based majority logic gate multiplier202211,374,574Linear input and non-linear output threshold logic gate202211,374,575Majority logic gate with non-linear input capacitors and conditioning logic202211,296,708Low power ferroelectric based majority logic gate adder202211,290,111Majority logic gate based and-or-invert logic gate with non-linear input capacitors202211,289,497Integration method of ferroelectric memory array202211,290,112Majority logic gate based XOR logic gate with non-linear input capacitors202211,283,453Low power ferroelectric based majority logic gate carry propagate and serial adder202211,277,137Majority logic gate with non-linear input capacitors202211,165,430Majority logic gate based sequential circuit202111,139,270Artificial intelligence processor with three-dimensional stacked memory2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to KEPLER COMPUTING INC (52)· patent assignee history
2021–2025Based in US· patent location history
2025Patents assigned to GOSAVI TANAY A (1)· patent assignee history
2025Patents assigned to HOLTZ MEGAN E (1)· patent assignee history
2025Patents assigned to LIN CHIA CHING (1)· patent assignee history
2025Patents assigned to MANIPATRUNI SASIKANTH (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| KEPLER COMPUTING INC | 52 | 2021–2025 |
| GOSAVI TANAY A | 1 | 2025 |
| HOLTZ MEGAN E | 1 | 2025 |
| LIN CHIA CHING | 1 | 2025 |
| MANIPATRUNI SASIKANTH | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 53 | 2021–2025 |