Inventor
Adam Brand
Inventor
Palo Alto, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices28%
H01LSemiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H01JElectric discharge tubes or discharge lamps3%
B08BCleaning in general2%
B23KSoldering or unsoldering2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H03KPulse technique2%
PatentTitleYear
11,043,380Techniques to engineer nanoscale patterned features using ions202110,622,452Transistors with dual gate conductors, and associated methods202010,573,744Self-aligned, dual-gate LDMOS transistors and associated methods202010,134,585Low temperature atomic layer deposition of oxides on compound semiconductors201810,109,534Multi-threshold voltage (Vt) workfunction metal by selective atomic layer deposition (ALD)201810,008,384Techniques to engineer nanoscale patterned features using ions20189,934,981Techniques for processing substrates using directional reactive ion etching20189,673,277'Methods and apparatus for forming horizontal gate all around device structures'20179,378,941'Interface treatment of semiconductor surfaces with high density low energy plasma'20169,337,314'Technique for selectively processing three dimensional device'20169,190,498'Technique for forming a FinFET device using selective ion implantation'20159,018,054'Metal gate structures for field effect transistors and method of fabrication'20158,999,829'Dual gate process'20158,999,821'Fin formation by epitaxial deposition'20158,864,915'Cleaning methods for improved photovoltaic module efficiency'20146,388,475'Voltage tolerant high drive pull-up driver for an I/O buffer'20026,287,908'Transistor device configurations for high voltage applications and improved device performance'20016,172,401'Transistor device configurations for high voltage applications and improved device performance'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2002Patents assigned to INTEL CORP (3)· patent assignee history
2001–2002Based in Mountain View, CA, US· patent location history
2014–2018Patents assigned to APPLIED MATERIALS INC (8)· patent assignee history
2014–2015Patents assigned to BRAND ADAM (2)· patent assignee history
2014–2021Based in Palo Alto, CA, US· patent location history
2018–2021Patents assigned to VARIAN SEMICONDUCTOR EQUIPMENT ASS INC (3)· patent assignee history
2018Based in Sunnyvale, CA, US· patent location history
2018Based in Los Alto, CA, US· patent location history
2020Patents assigned to MAXIM INTEGRATED PRODUCTS (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 8 | 2014–2018 |
| INTEL CORP | 3 | 2001–2002 |
| VARIAN SEMICONDUCTOR EQUIPMENT ASS INC | 3 | 2018–2021 |
| BRAND ADAMself | 2 | 2014–2015 |
| MAXIM INTEGRATED PRODUCTS | 2 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 13 | 2014–2021 |
| Mountain View, California, US | 3 | 2001–2002 |
| Sunnyvale, California, US | 1 | 2018 |
| Los Alto, California, US | 1 | 2018 |