LexDanaLexDanabeta
Inventor

Ivan Pavisic

Inventor
San Jose, CA, US

Overview

55→
Patents
1998–2015
Patent span
Physics
Primary field (CPC G)

Patents· 55 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing84%
G11CStatic stores6%
G01RMeasuring electric variables3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H01LSemiconductor devices2%
H03KPulse technique2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
9,024,657'Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller'20158,516,425'Method and computer program for generating grounded shielding wires for signal wiring'20138,239,813'Method and apparatus for balancing signal delay skew'20127,996,804'Signal delay skew reduction system'20117,818,703'Density driven layout for RRAM configuration module'20107,667,494'Methods and apparatus for fast unbalanced pipeline architecture'20107,546,505'Built in self test transport controller architecture'20097,356,785'Optimizing IC clock structures by minimizing clock uncertainty'20087,334,204'System for avoiding false path pessimism in estimating net delay for an integrated circuit design'20087,246,337'Density driven layout for RRAM configuration module'20077,243,324'Method of buffer insertion to achieve pin specific delays'20077,207,026'Memory tiling architecture'20077,194,717'Compact custom layout for RRAM column controller'20077,096,442'Optimizing IC clock structures by minimizing clock uncertainty'20067,093,228'Method and system for classifying an integrated circuit for optical proximity correction'20067,028,274'RRAM backend flow'20066,941,533'Clock tree synthesis with skew for memory devices'20056,901,571'Timing-driven placement method utilizing novel interconnect delay model'20056,810,515'Process of restructuring logics in ICs for setup and hold time optimization'20046,804,811'Process for layout of memory matrices in integrated circuits'20046,760,896'Process layout of buffer modules in integrated circuits'20046,757,881'Power routing with obstacles'20046,757,877'System and method for identifying and eliminating bottlenecks in integrated circuit designs'20046,701,493'Floor plan tester for integrated circuit design'20046,637,016'Assignment of cell coordinates'20036,629,304'Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells'20036,615,397'Optimal clock timing schedule for an integrated circuit'20036,557,144'Netlist resynthesis program based on physical delay calculation'20036,553,551'Timing recomputation'20036,550,045'Changing clock delays in an integrated circuit for skew optimization'20036,550,044'Method in integrating clock tree synthesis and timing optimization for an integrated circuit design'20036,546,539'Netlist resynthesis program using structure co-factoring'20036,546,541'Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances'20036,526,553'Chip core size estimation'20036,487,697'Distribution dependent clustering in buffer insertion of high fanout nets'20026,470,487'Parallelization of resynthesis'20026,463,572'IC timing analysis with known false paths'20026,412,102'Wire routing optimization'20026,292,924'Modifying timing graph to avoid given set of paths'20016,292,929'Advanced modular cell placement system'20016,269,469'Method and apparatus for parallel routing locking mechanism'20016,186,676'Method and apparatus for determining wire routing'20016,182,272'Metal layer assignment'20016,123,736'Method and apparatus for horizontal congestion removal'20006,075,933'Method and apparatus for continuous column density optimization'20006,068,662'Method and apparatus for congestion removal'20006,070,108'Method and apparatus for congestion driven placement'20006,067,409'Advanced modular cell placement system'20006,058,254'Method and apparatus for vertical congestion removal'20006,038,385'Physical design automation system and process for designing integrated circuit chip using \"chessboard\" and \"jiggle\" optimization'20006,000,038'Parallel processing of Integrated circuit pin arrival times'19995,898,597'Integrated circuit floor plan optimization system'19995,875,118'Integrated circuit cell placement parallelization with minimal number of conflicts'19995,859,782'Efficient multiprocessing for cell placement of integrated circuits'19995,796,625'Physical design automation system and process for designing integrated circuit chip using simulated annealing with \"chessboard and jiggle\" optimization'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2008Patents assigned to LSI LOGIC CORP (45)· patent assignee history
1998–2005Based in Cupertino, CA, US· patent location history
2001–2015Based in San Jose, CA, US· patent location history
2007–2013Patents assigned to LSI CORP (8)· patent assignee history
2012–2013Patents assigned to BHUTANI SANDEEP (2)· patent assignee history
2012–2013Patents assigned to KONG CHENG-GANG (2)· patent assignee history
2012–2013Patents assigned to KUCHERENKO IGOR (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LSI LOGIC CORP451998–2008
LSI CORP82007–2013
BHUTANI SANDEEP22012–2013
KONG CHENG-GANG22012–2013
KUCHERENKO IGOR22012–2013
Locations
LocationPatentsSpan
San Jose, California, US382001–2015
Cupertino, California, US171998–2005