Inventor
Harm Peter Hofstee
Inventor
Austin, TX, US
Overview
Patents· 109 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing64%
H04LTransmission of digital information, e.g. telegraphic communication16%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H03KPulse technique3%
H03MCoding2%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
G11CStatic stores1%
G01RMeasuring electric variables1%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
PatentTitleYear
10,719,399System combining efficient reliable storage and deduplication20209,703,516'Configurable interface controller'20179,361,160'Virtualization across physical partitions of a multi-core processor (MCP)'20168,918,553'Multithreaded programmable direct memory access engine'20148,838,950'Security architecture for system on chip'20148,830,714'High speed large scale dictionary matching'20148,824,569'High bandwidth decompression of variable length encoded data streams'20148,804,852'High bandwidth decompression of variable length encoded data streams'20148,775,840'Virtualization in a multi-core processor (MCP)'20148,732,716'Virtualization across physical partitions of a multi-core processor (MCP)'20148,704,686'High bandwidth compression to encoded data streams'20148,677,101'Method and apparatus for cooperative software multitasking in a processor system with a partitioned register file'20148,677,136'Authenticating messages using cryptographic algorithm constants supplied to a storage-constrained target'20148,566,576'Run-ahead approximated computations'20138,516,272'Secure dynamically reconfigurable logic'20138,510,546'Run-ahead approximated computations'20138,438,658'Providing sealed storage in a data processing device'20138,438,404'Main processing element for delegating virtualized control threads controlling clock speed and power consumption to groups of sub-processing elements in a system such that a group of sub-processing elements can be designated as pseudo main processing element'20138,341,638'Delegated virtualization across physical partitions of a multi-core processor (MCP)'20128,295,056'Silicon carrier structure and method of forming same'20128,261,117'Virtualization in a multi-core processor (MCP)'20128,229,989'Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units'20128,230,136'Multithreaded programmable direct memory access engine'20128,136,061'Method of logic circuit synthesis and design using a dynamic circuit library'20128,108,564'System and method for a configurable interface controller'20128,091,078'Dynamically partitioning processing across a plurality of heterogeneous processors'20128,086,865'Supplying cryptographic algorithm constants to a storage-constrained target'20118,032,849'Integrated circuit chip with modular design'20118,024,574'Unidirectional message masking and validation system and method'20117,953,951'Systems and methods for time division multiplex multithreading'20117,900,086'Accelerating test, debug and failure analysis of a multiprocessor device'20117,890,561'Random number generator'20117,870,309'Multithreaded programmable direct memory access engine'20117,836,222'System and method for tracking messages between a processing unit and an external device'20107,730,279'System for limiting the size of a local storage of a processor'20107,720,982'Computer architecture and software cells for broadband networks'20107,689,783'System and method for sharing memory by heterogeneous processors'20107,650,491'Method and system for controlled distribution of application code and content data within a computer network'20107,620,951'Hiding memory latency'20097,617,338'Memory with combined line and word access'20097,603,703'Method and system for controlled distribution of application code and content data within a computer network'20097,546,393'System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups'20097,533,238'Method for limiting the size of a local storage of a processor'20097,509,457'Non-homogeneous multi-processor system with shared memory'20097,496,673'SIMD-RISC microprocessor architecture'20097,493,357'Random carry-in for floating-point operations'20097,475,257'System and method for selecting and using a signal processor in a multiprocessor system to operate as a security for encryption/decryption of data'20097,469,332'Systems and methods for adaptively mapping an instruction cache'20087,446,588'Highly scalable methods and apparatus for multiplexing signals'20087,447,725'Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units'20087,409,520'Systems and methods for time division multiplex multithreading'20087,406,589'Processor having efficient function estimate instructions'20087,398,482'Modular design method and apparatus'20087,392,511'Dynamically partitioning processing across plurality of heterogeneous processors'20087,389,419'Methods for supplying cryptographic algorithm constants to a storage-constrained target'20087,363,609'Method of logic circuit synthesis and design using a dynamic circuit library'20087,321,958'System and method for sharing memory by heterogeneous processors'20087,299,371'Hierarchical management for multiprocessor system'20077,299,372'Hierarchical management for multiprocessor system with real-time attributes'20077,279,996'Method of functionality testing for a ring oscillator'20077,233,212'Oscillator array with row and column control'20077,233,998'Computer architecture and software cells for broadband networks'20077,200,688'System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command'20077,197,655'Lowered PU power usage method and apparatus'20077,174,410'Method, apparatus and computer program product for write data transfer'20077,120,748'Software-controlled cache set management'20067,114,035'Software-controlled cache set management with software-generated class identifiers'20067,103,748'Memory management for real-time applications'20067,093,080'Method and apparatus for coherent memory structure of heterogeneous processor systems'20067,051,168'Method and apparatus for aligning memory write data in a microprocessor'20067,043,579'Ring-topology based multiprocessor data access bus'20066,996,233'System and method for encrypting and verifying messages using three-phase encryption'20066,982,954'Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus'20066,983,387'Microprocessor chip simultaneous switching current reduction method and apparatus'20066,981,072'Memory management in multiprocessor system'20056,970,982'Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions'20056,941,335'Random carry-in for floating-point operations'20056,924,802'Efficient function interpolation using SIMD vector permute functionality'20056,915,506'Method and apparatus for evaluating results of multiple software tools'20056,907,477'Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors'20056,865,631'Reduction of interrupts in remote procedure calls'20056,839,828'SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode'20056,836,849'Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements'20046,826,110'Cell circuit for multiport memory using decoder'20046,820,142'Token based DMA'20046,793,123'Packaging for multi-processor shared-memory system'20046,785,841'Processor with redundant logic'20046,779,049'Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism'20046,772,368'Multiprocessor with pair-wise high reliability mode, and method therefore'20046,760,819'Symmetric multiprocessor coherence mechanism'20046,751,749'Method and apparatus for computer system reliability'20046,728,872'Method and apparatus for verifying that instructions are pipelined in correct architectural sequence'20046,717,882'Cell circuit for multiport memory using 3-way multiplexer'20046,708,267'System and method in a pipelined processor for generating a single cycle pipeline stall'20046,675,182'Method and apparatus for performing rotate operations using cascaded multiplexers'20046,629,235'Condition code register architecture for supporting multiple execution units'20036,600,959'Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays'20036,598,153'Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions'20036,587,941'Processor with improved history file mechanism for restoring processor state after an exception'20036,541,847'Packaging for multi-processor shared-memory system'20036,507,115'Multi-chip integrated circuit module'20036,502,224'Method and apparatus for synthesizing levelized logic'20026,430,672'Method for performing address mapping using two lookup tables'20026,335,650'Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages'20026,268,660'Silicon packaging with through wafer interconnects'20016,212,619'System and method for high-speed register renaming by counting'20016,138,208'Multiple level cache memory with overlapped L1 and L2 memory access'20006,038,659'Method for using read-only memory to generate controls for microprocessor'20006,014,763'At-speed scan testing'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2020Patents assigned to IBM (108)· patent assignee history
2000–2020Based in Austin, TX, US· patent location history
2011–2017Patents assigned to HOFSTEE HARM PETER (10)· patent assignee history
2012–2014Patents assigned to HOFSTEE HARM P (10)· patent assignee history
2012–2014Patents assigned to DUVALSAINT KARL J (5)· patent assignee history
2012–2014Patents assigned to KIM DAEIK (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 108 | 2000–2020 |
| HOFSTEE HARM Pself | 10 | 2012–2014 |
| HOFSTEE HARM PETERself | 10 | 2011–2017 |
| DUVALSAINT KARL J | 5 | 2012–2014 |
| KIM DAEIK | 5 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 109 | 2000–2020 |