Inventor

Christopher F. Lyons

Inventor
Fremont, CA, US

Overview

147→
Patents
1983–2014
Patent span
Electricity
Primary field (CPC H)

Patents· 147 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices18%
H10DInorganic electric semiconductor devices9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
B82YSpecific uses or applications of nanostructures5%
H10KOrganic electric solid-state devices4%
G11CStatic stores3%
H10BElectronic memory devices2%
C23CCoating metallic material1%
PatentTitleYear
8,748,800'Charge storage device for detecting alpha particles'20148,436,289'System and method for detecting particles with a semiconductor device'20137,608,855'Polymer dielectrics for memory element array interconnect'20097,427,457'Methods for designing grating structures for use in situ scatterometry to detect photoresist defects'20087,268,066'Method for semiconductor gate line dimension reduction'20077,169,711'Method of using carbon spacers for critical dimension (CD) reduction'20077,125,652'Immersion lithographic process using a conforming immersion medium'20067,122,455'Patterning with rigid organic under-layer'20067,115,440'SO2 treatment of oxidized CuO for copper sulfide formation of memory element growth'20067,112,489'Negative resist or dry develop process for forming middle of line implant layer'20067,056,804'Shallow trench isolation polish stop layer for reduced topography'20067,052,921'System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process'20067,018,922'Patterning for elongated VSS contact flash memory'20067,015,504'Sidewall formation for high density polymer memory element array'20067,011,762'Metal bridging monitor for etch and CMP endpoint detection'20067,008,832'Damascene process for a T-shaped gate electrode'20066,989,332'Ion implantation to modulate amorphous carbon stress'20066,982,043'Scatterometry with grating to observe resist removal rate during etch'20066,972,576'Electrical critical dimension measurement and defect detection for reticle fabrication'20056,955,939'Memory element formation with photosensitive polymer dielectric'20056,906,777'Pellicle for a lithographic lens'20056,900,124'Patterning for elliptical Vss contact on flash memory'20056,878,961'Photosensitive polymeric memory elements'20056,869,734'EUV reflective mask having a carbon film and a method of making such a mask'20056,869,888'E-beam flood exposure of spin-on material to eliminate voids in vias'20056,864,556'CVD organic polymer film for advanced gate patterning'20056,864,024'Real-time control of chemically-amplified resist processing on wafer'20056,852,455'Amorphous carbon absorber/shifter film for attenuated phase shift mask'20056,849,530'Method for semiconductor gate line dimension reduction'20056,836,398'System and method of forming a passive layer by a CMP process'20046,829,040'Lithography contrast enhancement technique by varying focus with wavelength modulation'20046,825,114'Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning'20046,825,060'Photosensitive polymeric memory elements'20046,808,591'Model based metal overetch control'20046,803,267'Silicon containing material for patterning polymeric memory element'20046,790,790'High modulus filler for low k materials'20046,787,458'Polymer memory device formed in via opening'20046,773,954'Methods of forming passive layers in organic memory cells'20046,773,998'Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning'20046,771,356'Scatterometry of grating structures to monitor wafer stress'20046,764,949'Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication'20046,753,266'Method of enhancing gate patterning properties with reflective hard mask'20046,740,566'Ultra-thin resist shallow trench process using high selectivity nitride etch'20046,737,222'Dual damascene process utilizing a bi-layer imaging layer'20046,689,541'Process for forming a photoresist mask'20046,686,270'Dual damascene trench depth monitoring'20046,684,172'Sensor to predict void free films using various grating structures and characterize fill performance'20046,660,645'Process for etching an organic dielectric using a silyated photoresist mask'20036,656,763'Spin on polymers for organic memory devices'20036,654,660'Controlling thermal expansion of mask substrates by scatterometry'20036,654,659'Quartz crystal monitor wafer for lithography and etch process monitoring'20036,635,409'Method of strengthening photoresist to prevent pattern collapse'20036,627,360'Carbonization process for an etch mask'20036,623,893'Pellicle for use in EUV lithography and a method of making such a pellicle'20036,624,642'Metal bridging monitor for etch and CMP endpoint detection'20036,605,546'Dual bake for BARC fill without voids'20036,605,855'CVD plasma process to fill contact hole in damascene process'20036,605,413'Chemical treatment to strengthen photoresists to prevent pattern collapse'20036,599,810'Shallow trench isolation formation with ion implantation'20036,593,035'Pellicle for use in small wavelength lithography and a method for making such a pellicle using polymer films'20036,589,711'Dual inlaid process using a bilayer resist'20036,566,214'Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer'20036,563,221'Connection structures for integrated circuits and processes for their formation'20036,558,965'Measuring BARC thickness using scatterometry'20036,548,423'Multilayer anti-reflective coating process for integrated circuit fabrication'20036,544,693'Pellicle for use in small wavelength lithography and a method for making such a pellicle'20036,544,885'Polished hard mask process for conductor layer patterning'20036,541,360'Bi-layer trim etch process to form integrated circuit gate structures'20036,534,418'Use of silicon containing imaging layer to define sub-resolution gate structures'20036,528,372'Sidewall spacer definition of gates'20036,458,691'Dual inlaid process using an imaging layer to protect via from poisoning'20026,448,164'Dark field image reversal for gate or line patterning'20026,440,640'Thin resist with transition metal hard mask for via etch application'20026,423,650'Ultra-thin resist coating quality by increasing surface roughness of the substrate'20026,423,475'Sidewall formation for sidewall patterning of sub 100 nm structures'20026,417,084'T-gate formation using a modified conventional poly process'20026,403,456'T or T/Y gate formation using trim etch processing'20026,399,284'Sub-lithographic contacts and vias through pattern, CVD and etch back processing'20026,391,525'Sidewall patterning for sub 100 nm gate conductors'20026,383,952'RELACS process to double the frequency or pitch of small feature formation'20026,380,588'Semiconductor device having uniform spacers'20026,380,067'Method for creating partially UV transparent anti-reflective coating for semiconductors'20026,380,047'Shallow trench isolation formation with two source/drain masks and simplified planarization mask'20026,358,856'Bright field image reversal for contact hole patterning'20026,350,559'Method for creating thinner resist coating that also has fewer pinholes'20026,326,231'Use of silicon oxynitride ARC for metal layers'20016,326,319'Method for coating ultra-thin resist films'20016,319,843'Nitride surface passivation for acid catalyzed chemically amplified resist processing'20016,319,802'T-gate formation using modified damascene processing with two masks'20016,316,277'Tuning substrate/resist contrast to maximize defect inspection sensitivity for ultra-thin resist in DUV lithography'20016,313,019'Y-gate formation using damascene processing'20016,309,926'Thin resist with nitride hard mask for gate etch application'20016,306,560'Ultra-thin resist and SiON/oxide hard mask for metal etch'20016,291,137'Sidewall formation for sidewall patterning of sub 100 nm structures'20016,287,959'Deep submicron metallization using deep UV photoresist'20016,270,929'Damascene T-gate using a relacs flow'20016,255,202'Damascene T-gate using a spacer flow'20016,245,493'Method for reducing surface reflectivity by increasing surface roughness'20016,239,031'Stepper alignment mark structure for maintaining alignment integrity'20016,214,737'Simplified sidewall formation for sidewall patterning of sub 100 nm structures'20016,210,050'Resist developing method and apparatus with nozzle offset for uniform developer application'20016,200,907'Ultra-thin resist and barrier metal/oxide hard mask for metal etch'20016,187,666'CVD plasma process to fill contact hole in damascene process'20016,183,938'Conformal organic coatings for sidewall patterning of sublithographic structures'20016,184,128'Method using a thin resist mask for dual damascene stop layer etch'20016,171,962'Shallow trench isolation formation without planarization mask'20016,171,763'Ultra-thin resist and oxide/nitride hard mask for metal etch'20016,165,695'Thin resist with amorphous silicon hard mask for via etch application'20006,162,587'Thin resist with transition metal hard mask for via etch application'20006,162,699'Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery'20006,156,658'Ultra-thin resist and silicon/oxide hard mask for metal etch'20006,156,480'Low defect thin resist processing for deep submicron lithography'20006,143,624'Shallow trench isolation formation with spacer-assisted ion implantation'20006,140,023'Method for transferring patterns created by lithography'20006,130,467'Shallow trench isolation with spacers for improved gate oxide quality'20006,127,070'Thin resist with nitride hard mask for via etch application'20006,127,089'Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques'20006,124,183'Shallow trench isolation formation with simplified reverse planarization mask'20006,121,123'Gate pattern formation using a BARC as a hardmask'20006,114,235'Multipurpose cap layer dielectric'20006,103,611'Methods and arrangements for improved spacer formation within a semiconductor device'20006,090,713'Shallow trench isolation formation with simplified reverse planarization mask'20006,090,712'Shallow trench isolation formation with no polish stop'20006,087,271'Methods for removal of an anti-reflective coating following a resist protect etching process'20006,074,927'Shallow trench isolation formation with trench wall spacer'20006,057,206'Mark protection scheme with no masking'20006,057,080'Top antireflective coating film'20006,037,671'Stepper alignment mark structure for maintaining alignment integrity'20006,020,269'Ultra-thin resist and nitride/oxide hard mask for metal etch'20005,990,524'Silicon oxime spacer for preventing over-etching during local interconnect formation'19995,970,363'Shallow trench isolation formation with improved trench edge oxide'19995,970,362'Simplified shallow trench isolation formation with no polish stop'19995,963,841'Gate pattern formation using a bottom anti-reflective coating'19995,930,645'Shallow trench isolation formation with reduced polish stop thickness'19995,910,337'Phase-averaging resist coating for reflectivity control'19995,821,036'Method of developing positive photoresist and compositions therefor'19985,807,790'Selective i-line BARL etch process'19985,744,537'Antireflective coating films'19985,554,485'Mid and deep-UV antireflection coatings and methods for use thereof'19965,482,817'Mid and deep-uv antireflection coatings and methods for use thereof'19965,401,614'Mid and deep-UV antireflection coatings and methods for use thereof'19955,380,621'Mid and deep-UV antireflection coatings and methods for use thereof'19955,273,856'Positive working photoresist composition containing mid or near UV radiation sensitive quinone diazide and sulfonic acid ester of imide or oxime which does not absorb mid or near UV radiation'19935,240,812'Top coat for acid catalyzed resists'19935,227,280'Resists with enhanced sensitivity and contrast'19934,474,864'Method for dose calculation of photolithography projection printers through bleaching of photo-active compound in a photoresist'19844,379,830'Developer for positive photolithographic articles'1983

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1983Based in Wappingers Falls, NY, US· patent location history
1984–2000Patents assigned to IBM (11)· patent assignee history
1984–1999Based in Lagrangeville, NY, US· patent location history
1993Based in La Grangeville, NY, US· patent location history
1998–2008Patents assigned to ADVANCED MICRO DEVICES INC (130)· patent assignee history
1998Patents assigned to CLARIANT FINANCE BVI LTD (1)· patent assignee history
1998–2014Based in Fremont, CA, US· patent location history
1998–2000Based in Freemont, CA, US· patent location history
2009–2014Patents assigned to SPANSION LLC (3)· patent assignee history
2013Patents assigned to CLOPTON PATRICK MARK (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ADVANCED MICRO DEVICES INC1301998–2008
IBM111984–2000
SPANSION LLC32009–2014
CLARIANT FINANCE BVI LTD11998
CLOPTON PATRICK MARK12013
Locations
LocationPatentsSpan
Fremont, California, US1341998–2014
Lagrangeville, New York, US91984–1999
Freemont, California, US21998–2000
La Grangeville, New York, US11993
Wappingers Falls, New York, US11983