Inventor
Shiang Yang Ong
Inventor
Singapore, SG
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices43%
H01LSemiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
PatentTitleYear
10,529,819High voltage Schottky diode and manufacturing method thereof202010,510,831Low on resistance high voltage metal oxide semiconductor transistor201910,504,768Contact structures to deep trench isolation structures and method of nanufacturing the same20199,831,304Integrated circuits with deep trench isolations and methods for producing the same20179,673,084'Isolation scheme for high voltage device'20178,999,803'Methods for fabricating integrated circuits with the implantation of fluorine'20158,975,704'Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations'20158,975,708'Semiconductor device with reduced contact resistance and method of manufacturing thereof'20158,936,977'Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations'20158,916,430'Methods for fabricating integrated circuits with the implantation of nitrogen'20148,828,834'Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process'20148,703,578'Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations'20148,470,700'Semiconductor device with reduced contact resistance and method of manufacturing thereof'20138,440,530'Methods of forming highly scaled semiconductor devices using a disposable spacer technique'20138,143,651'Nested and isolated transistors with reduced impedance difference'20128,008,744'Selective STI stress relaxation through ion implantation'20117,767,577'Nested and isolated transistors with reduced impedance difference'20107,727,856'Selective STI stress relaxation through ion implantation'20107,400,018'End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping'20087,109,099'End of range (EOR) secondary defect engineering using substitutional carbon doping'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2010Patents assigned to CHARTERED SEMICONDUCTOR MFG (4)· patent assignee history
2006–2020Based in Singapore, SG· patent location history
2011–2020Patents assigned to GLOBALFOUNDRIES SG PTE LTD (14)· patent assignee history
2012–2015Patents assigned to ONG SHIANG YANG (6)· patent assignee history
2013–2015Patents assigned to HOENTSCHEL JAN (4)· patent assignee history
2013–2015Patents assigned to FLACHOWSKY STEFAN (3)· patent assignee history
2013–2015Based in Dresden, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES SG PTE LTD | 14 | 2011–2020 |
| ONG SHIANG YANGself | 6 | 2012–2015 |
| CHARTERED SEMICONDUCTOR MFG | 4 | 2006–2010 |
| HOENTSCHEL JAN | 4 | 2013–2015 |
| FLACHOWSKY STEFAN | 3 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Singapore, SG | 15 | 2006–2020 |
| Dresden, DE | 5 | 2013–2015 |