Inventor
Naoya Kanda
Inventor
Fujisawa, JP
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1039%
H05KPrinted circuits12%
G06KGraphical data reading10%
Y10TTechnical subjects covered by former us classification9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
C23CCoating metallic material6%
C04BLime, magnesia3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y02PClimate change mitigation technologies in the production or processing of goods3%
B23KSoldering or unsoldering1%
PatentTitleYear
8,035,522'RFID tag'20118,009,047'RFID tag'20117,754,581'Method for manufacturing a three-dimensional semiconductor device and a wafer used therein'20107,615,870'Semiconductor device, manufacturing method thereof, and connection method of circuit board'20097,413,130'Paper tag identified by using radiofrequency and method of manufacturing the same'20087,190,072'RFID-chip having RFID-tag or magnifying electrode'20077,185,823'Paper tag identified by using radiofrequency and method of manufacturing the same'20077,141,451'Wireless communication medium and method of manufacturing the same'20067,122,087'Method of manufacturing RFID'20067,084,498'Semiconductor device having projected electrodes and structure for mounting the same'20067,057,283'Semiconductor device and method for producing the same'20067,002,250'Semiconductor module'20066,930,388'Semiconductor device and method for manufacturing the same and semiconductor device-mounted structure'20056,822,317'Semiconductor apparatus including insulating layer having a protrusive portion'20046,791,178'Multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices'20046,780,748'Method of fabricating a wafer level chip size package utilizing a maskless exposure'20046,770,547'Method for producing a semiconductor device'20046,624,504'Semiconductor device and method for manufacturing the same'20036,610,934'Semiconductor module and method of making the device'20036,589,802'Packaging structure and method of packaging electronic parts'20036,153,938'Flip-chip connecting method, flip-chip connected structure and electronic device using the same'20005,811,877'Semiconductor device structure'19985,476,726'Circuit board with metal layer for solder bonding and electronic circuit device employing the same'19955,202,151'Electroless gold plating solution, method of plating with gold by using the same, and electronic device plated with gold by using the same'19935,191,624'Optical information storing apparatus and method for production of optical deflector'19935,178,738'Ion-beam sputtering apparatus and method for operating the same'19935,089,104'Method and apparatus for forming a multiple-element thin film based on ion beam sputtering'19925,086,337'Connecting structure of electronic part and electronic device using the structure'19924,963,974'Electronic device plated with gold by means of an electroless gold plating solution'19904,935,285'Ceramic substrates for microelectronic circuits and process for producing same'19904,922,377'Module and a substrate for the module'19904,913,769'Process for preparing superconductive wiring board'19904,817,276'Process for producing ceramic substrates for microelectronic circuits'19894,734,233'Ceramic wiring substrate and process for producing the same'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–2011Patents assigned to HITACHI LTD (27)· patent assignee history
1988–1993Based in Yokohama, JP· patent location history
1992–2000Based in Yokosuka, JP· patent location history
2003–2011Based in Fujisawa, JP· patent location history
2004–2006Patents assigned to RENESAS TECH CORP (5)· patent assignee history
2009–2010Patents assigned to ELPIDA MEMORY INC (2)· patent assignee history
2009–2010Based in Tokyo, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI LTD | 27 | 1988–2011 |
| RENESAS TECH CORP | 5 | 2004–2006 |
| ELPIDA MEMORY INC | 2 | 2009–2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fujisawa, JP | 18 | 2003–2011 |
| Yokohama, JP | 8 | 1988–1993 |
| Yokosuka, JP | 6 | 1992–2000 |
| Tokyo, JP | 2 | 2009–2010 |