Inventor

Su Tao

Inventor

Kaohsiung, TW

Overview

1995–2009

Patent span

Electricity

Primary field (CPC H)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1058%

H05KPrinted circuits7%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%

B23KSoldering or unsoldering5%

G01RMeasuring electric variables3%

Y10TTechnical subjects covered by former us classification3%

B81BMicrostructural devices or systems, e.g. micromechanical devices2%

B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%

F04CRotary-piston, or oscillating-piston, positive-displacement machines for liquids2%

G02BOptical elements, systems or apparatus2%

PatentTitleYear

7,605,020'Semiconductor chip package'2009 7,473,581'Wafer stacking package method'2009 7,321,168'Semiconductor package and method for manufacturing the same'2008 7,291,926'Multi-chip package structure'2007 7,253,529'Multi-chip package structure'2007 7,168,352'Process for sawing substrate strip'2007 7,151,308'Semiconductor chip package'2006 7,141,867'Quad flat non-leaded package'2006 7,129,583'Multi-chip package structure'2006 7,102,241'Leadless semiconductor package'2006 7,064,428'Wafer-level package structure'2006 7,037,759'Semiconductor package and method for manufacturing the same'2006 7,023,082'Semiconductor package and manufacturing method thereof'2006 7,009,302'Micromachine package and method for manufacturing the same'2006 7,002,805'Thermal enhance MCM package and manufacturing method thereof'2006 7,002,257'Optical component package and packaging including an optical component horizontally attached to a substrate'2006 6,967,153'Bump fabrication process'2005 6,946,729'Wafer level package structure with a heat slug'2005 6,939,790'Wafer bumping process with solder balls bonded to under bump metallurgy layer formed over active surface by forming flux on solder ball surfaces and reflowing the solder'2005 6,933,605'Semiconductor package'2005 6,927,964'Structure for preventing burnt fuse pad from further electrical connection'2005 6,908,842'Bumping process'2005 6,891,274'Under-bump-metallurgy layer for improving adhesion'2005 6,877,653'Method of modifying tin to lead ratio in tin-lead bump'2005 6,864,168'Bump and fabricating process thereof'2005 6,846,719'Process for fabricating wafer bumps'2005 6,838,762'Water-level package with bump ring'2005 6,822,324'Wafer-level package with a cavity and fabricating method thereof'2004 6,819,002'Under-ball-metallurgy layer'2004 6,809,852'Microsystem package structure'2004 6,768,207'Multichip wafer-level package and method for manufacturing the same'2004 6,768,332'Semiconductor wafer and testing method for the same'2004 6,756,256'Method for preventing burnt fuse pad from further electrical connection'2004 6,732,912'Solder ball attaching process'2004 6,720,244'Bump fabrication method'2004 6,713,320'Bumping process'2004 6,692,581'Solder paste for fabricating bump'2004 6,693,364'Optical integrated circuit element package and process for making the same'2004 6,664,128'Bump fabrication process'2003 6,617,237'Lead-free bump fabrication process'2003 6,610,924'Semiconductor package'2003 6,573,123'Semiconductor chip package and manufacturing method thereof'2003 6,534,852'Ball grid array semiconductor package with improved strength and electric performance and method for making the same'2003 6,528,393'Method of making a semiconductor package by dicing a wafer from the backside surface thereof'2003 6,461,897'Multichip module having a stacked chip arrangement'2002 6,462,421'Multichip module'2002 6,392,424'Press plate of wire bond checking system'2002 6,369,439'Strip of semiconductor package'2002 6,359,340'Multichip module having a stacked chip arrangement'2002 6,348,729'Semiconductor chip package and manufacturing method thereof'2002 6,342,443'Method and structure for forming flip chip with collapse-controlled solder bumps on a substrate'2002 6,316,828'Structure of a solder mask for the circuit module of a BGA substrate'2001 6,313,413'Wire structure of substrate for layout detection'2001 6,312,976'Method for manufacturing leadless semiconductor chip package'2001 6,300,166'Method for packaging a BGA and the structure of a substrate for use with the method'2001 6,265,768'Chip scale package'2001 6,258,626'Method of making stacked chip package'2001 6,252,305'Multichip module having a stacked chip arrangement'2001 6,229,702'Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability'2001 6,215,193'Multichip modules and manufacturing method therefor'2001 6,211,574'Semiconductor package with wire protection and method therefor'2001 6,204,559'Ball grid assembly type semiconductor package having improved chip edge support to prevent chip cracking'2001 6,201,299'Substrate structure of BGA semiconductor package'2001 6,191,360'Thermally enhanced BGA package'2001 6,190,529'Method for plating gold to bond leads on a semiconductor substrate'2001 6,176,417'Ball bonding method on a chip'2001 6,176,416'Method of making low-profile wire connection'2001 6,172,318'Base for wire bond checking'2001 6,161,753'Method of making a low-profile wire connection for stacked dies'2000 6,153,939'Flip-chip semiconductor device with enhanced reliability and manufacturing efficiency, and the method for under filling the same'2000 6,150,730'Chip-scale semiconductor package'2000 6,135,522'Sucker for transferring packaged semiconductor device'2000 6,118,176'Stacked chip assembly utilizing a lead frame'2000 6,093,960'Semiconductor package having a heat spreader capable of preventing being soldered and enhancing adhesion and electrical performance'2000 6,048,184'Back-pressure sealing system for revolving compressor'2000 5,921,762'Oldham ring system for rotary fluid apparatus'1999 5,474,433'Axial sealing mechanism of volute compressor'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2000Patents assigned to IND TECH RES INST (3)· patent assignee history

1995Based in Gau-Shyong, TW· patent location history

1999Based in Hsinchu, TW· patent location history

2000–2009Patents assigned to ADVANCED SEMICONDUCTOR ENG (72)· patent assignee history

2000–2009Based in Kaohsiung, TW· patent location history

2002Patents assigned to ADVANCED SEMICONDCUTOR ENGINEE (1)· patent assignee history

2005–2007Based in Kaoshiung, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED SEMICONDUCTOR ENG	72	2000–2009
IND TECH RES INST	3	1995–2000
ADVANCED SEMICONDCUTOR ENGINEE	1	2002

Locations

Location	Patents	Span
Kaohsiung, TW	71	2000–2009
Kaoshiung, TW	4	2005–2007
Hsinchu, TW	1	1999
Gau-Shyong, TW	1	1995