Inventor

Martin Ostermayr

Inventor
Feldkirchen, DE

Overview

26→
Patents
2002–2019
Patent span
Electricity
Primary field (CPC H)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores31%
H10BElectronic memory devices27%
H10DInorganic electric semiconductor devices23%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices6%
H01LSemiconductor devices4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
10,347,312Memory circuit and method for operating a first MRAM and a second MRAM set of memory cells configured to operate in a direct access mode and/or refresh mode20199,824,737'Memory circuit and method for operating a first and a second set of memory cells in direct memory access mode with refresh'20178,853,791'SRAM memory cell having a dogleg shaped gate electrode structure'20148,846,462'Transistor level routing'20148,765,548'Capacitors and methods of manufacture thereof'20148,546,916'Capacitors and methods of manufacture thereof'20138,531,907'Semiconductor memory device and method'20138,518,820'Methods for forming contacts in semiconductor devices'20138,426,114'L-shaped feature, method of making an L-shaped feature and method of making an L-shaped structure'20138,223,573'Method and device for controlling a memory access and correspondingly configured semiconductor memory'20128,076,730'Transistor level routing'20117,995,366'Homogenous cell array'20117,816,198'Semiconductor device and method for manufacturing the same'20107,692,974'Memory cell, memory device, device and method of accessing a memory cell'20107,674,703'Gridded contacts in semiconductor devices'20107,675,799'Method of operating a memory cell, memory cell and memory unit'20107,655,563'Method for preventing the formation of dentrites in a semiconductor'20107,606,107'Memory cell, read device for memory cell, memory assembly, and corresponding method'20097,531,420'Semiconductor memory cell and corresponding method of producing same'20097,440,334'Multi-transistor memory cells'20087,394,682'Bit line dummy core-cell and method for producing a bit line dummy core-cell'20087,327,593'ROM memory cell having defined bit line voltages'20087,304,342'Semiconductor memory cell and associated fabrication method'20077,161,824'Method for programming a memory arrangement and programmed memory arrangement'20076,906,942'Programmable mask ROM building element and process of manufacture'20056,448,617'Semiconductor read-only memory configuration with substrate contacts and polysilicon bridge cells'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2014Patents assigned to INFINEON TECHNOLOGIES AG (24)· patent assignee history
2005–2013Based in Feldkirchen, DE· patent location history
2010Based in LaGrange, NY, US· patent location history
2011–2014Patents assigned to OSTERMAYR MARTIN (8)· patent assignee history
2011–2014Based in Beacon, NY, US· patent location history
2013Patents assigned to HAFFNER HENNING (1)· patent assignee history
2013Patents assigned to HEROLD KLAUS (1)· patent assignee history
2014Based in Bavaria, DE· patent location history
2017–2019Patents assigned to INTEL IP CORP (2)· patent assignee history
2017–2019Based in Oberhaching, DE· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INFINEON TECHNOLOGIES AG242002–2014
OSTERMAYR MARTINself82011–2014
INTEL IP CORP22017–2019
HAFFNER HENNING12013
HEROLD KLAUS12013
Locations
LocationPatentsSpan
Feldkirchen, DE112005–2013
Beacon, New York, US82011–2014
Oberhaching, DE22017–2019
LaGrange, New York, US22010
Bavaria, DE12014