Inventor
ROBERT L. SANKMAN
Inventor
US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H01LSemiconductor devices37%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H01FMagnets3%
H10DInorganic electric semiconductor devices3%
H01QAntennas, i.e. radio aerials2%
H01GCapacitors2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
H05KPrinted circuits1%
PatentTitleYear
12,592,334Stacked magnetic inductor and method202612,586,906Antenna package using ball attach array to connect antenna and base substrates202612,557,665Embedded semiconductive chips in reconstituted wafers, and systems containing same202612,476,174Ultra-thin, hyper-density semiconductor packages202512,476,235Multi-chip packaging202512,406,914Ultra-thin, hyper-density semiconductor packages202512,387,999Planar integrated circuit package interconnects202512,341,129Substrateless double-sided embedded multi-die interconnect bridge202512,334,242Coreless electronic substrates having embedded inductors202512,300,620Inorganic-based embedded-die layers for modular semiconductive devices202512,261,124Embedded die architecture and method of making202512,199,085Multi-chip packaging202512,142,568Multi-die ultrafine pitch patch architecture of interconnect bridge over glass layer and method of making202412,046,560Microelectronic device with embedded die substrate on interposer202412,002,745High performance integrated RF passives using dual lithography process202411,978,685Glass core patch with in situ fabricated fan-out layer to enable die tiling applications202411,923,257Hybrid microelectronic substrates202411,901,248Embedded die architecture and method of making202411,894,311Microelectronic device with embedded die substrate on interposer202411,894,359Distributed semiconductor die and package architecture202411,870,163Antenna package using ball attach array to connect antenna and base substrates202411,869,842Scalable high speed high bandwidth IO signaling package architecture and method of making202411,832,419Full package vapor chamber with IHS202311,817,444Multi-chip packaging202311,798,887Inorganic-based embedded-die layers for modular semiconductive devices202311,764,158Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same202311,756,889Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making202311,705,377Stacked die cavity package202311,694,959Multi-die ultrafine pitch patch architecture and method of making202311,626,395Thermal spreading management of 3D stacked integrated circuits202311,521,923Integrated circuit package supports202211,444,033Hybrid microelectronic substrate and methods for fabricating the same202211,430,740Microelectronic device with embedded die substrate on interposer202211,430,724Ultra-thin, hyper-density semiconductor packages202211,410,919Stacked silicon die architecture with mixed flipcip and wirebond interconnect202211,404,349Multi-chip packages and sinterable paste for use with thermal interface materials202211,355,849Antenna package using ball attach array to connect antenna and base substrates202211,348,911Multi-chip packaging202211,328,968Stacked die cavity package202211,276,630Planar integrated circuit package interconnects202211,257,688Embedded semiconductive chips in reconstituted wafers, and systems containing same202211,257,804Distributed semiconductor die and package architecture202211,227,825High performance integrated RF passives using dual lithography process202211,222,877Thermally coupled package-on-package semiconductor packages202211,201,128Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages202111,164,818Inorganic-based embedded-die layers for modular semiconductive devices2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (46)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 46 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 46 | 2021–2026 |