LexDanaLexDanabeta
Inventor

Manoj Dusanapudi

Inventor
Bangalore, IN

Overview

62→
Patents
2009–2021
Patent span
Physics
Primary field (CPC G)

Patents· 62 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing73%
G11CStatic stores17%
G06NComputing arrangements based on specific computational models5%
G01RMeasuring electric variables2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
11,094,391List insertion in test segments with non-naturally aligned data boundaries202111,061,821Method, system, and apparatus for stress testing memory translation tables202110,877,864Controlling segment layout in a stress test for a processor memory with a link stack202010,831,620Core pairing in multicore systems202010,748,637System and method for testing processor errors202010,713,179Efficiently generating effective address translations for memory management test cases202010,540,249Stress testing a processor memory with a link stack202010,521,355Method, system, and apparatus for stress testing memory translation tables201910,489,259Replicating test case data into a cache with non-naturally aligned data boundaries201910,489,261Efficient testing of direct memory address translation201910,481,991Efficient testing of direct memory address translation201910,438,682List insertion in test segments with non-naturally aligned data boundaries201910,346,314Efficiently generating effective address translations for memory management test cases201910,318,456Validation of correctness of interrupt triggers and delivery201910,318,667Test case generation201910,261,917Identifying stale entries in address translation cache201910,261,878Stress testing a processor memory with a link stack201910,241,880Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems201910,223,225Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries201910,169,180Replicating test code and test data into a cache with non-naturally aligned data boundaries201910,169,181Efficient validation of transactional memory in a computer processor201910,169,185Efficient testing of direct memory address translation201910,169,186Efficient testing of direct memory address translation201910,055,320Replicating test case data into a cache and cache inhibited memory201810,007,568Testing a non-core MMU20189,959,183Replicating test case data into a cache with non-naturally aligned data boundaries20189,959,182Replicating test case data into a cache with non-naturally aligned data boundaries20189,940,226Synchronization of hardware agents in a computer system20189,921,897'Testing a non-core MMU'20189,910,941'Test case generation'20189,892,060'Identifying stale entries in address translation cache'20189,720,845'Identifying stale entries in address translation cache'20179,697,138'Identifying stale entries in address translation cache'20179,612,929'Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems'20179,594,672'Test case generation'20179,594,680'Identifying stale entries in address translation cache'20179,542,290'Replicating test case data into a cache with non-naturally aligned data boundaries'20179,514,036'Test case generation'20169,501,408'Efficient validation of coherency between processor cores and accelerators in computer systems'20169,424,159'Performance measurement of hardware accelerators'20169,298,516'Verification of dynamic logical partitioning'20169,286,133'Verification of dynamic logical partitioning'20169,287,005'Detecting missing write to cache/memory operations'20169,128,887'Using a buffer to replace failed memory cells in a memory component'20159,043,569'Memory data management'20159,015,522'Implementing DRAM failure scenarios mitigation by using buffer techniques delaying usage of RAS features in computer systems'20158,832,502'Hardware verification using acceleration platform'20148,127,192'Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode'20128,099,559'System and method for generating fast instruction and data interrupts for processor design verification and validation'20128,019,566'System and method for efficiently testing cache congruence classes during processor design verification and validation'20118,006,221'System and method for testing multiple processor modes for processor design verification and validation'20117,992,059'System and method for testing a large memory area during processor design verification and validation'20117,966,521'Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics'20117,797,650'System and method for testing SLB and TLB cells during processor design verification and validation'20107,752,499'System and method for using resource pools and instruction pools for processor design verification and validation'20107,747,908'System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation'20107,739,570'System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation'20107,689,886'System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation'20107,669,083'System and method for re-shuffling test case instruction orders for processor design verification and validation'20107,661,023'System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation'20107,647,539'System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation'20107,584,394'System and method for pseudo-random test pattern memory allocation for processor design verification and validation'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2021Patents assigned to IBM (58)· patent assignee history
2009–2012Based in Karnataka, IN· patent location history
2010–2021Based in Bangalore, IN· patent location history
2012–2015Patents assigned to DUSANAPUDI MANOJ (4)· patent assignee history
2012–2014Patents assigned to KAPOOR SHAKTI (3)· patent assignee history
2012Patents assigned to HATTI SUNIL SURESH (2)· patent assignee history
2016Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
2019Based in Banglaore, IN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM582009–2021
DUSANAPUDI MANOJself42012–2015
GLOBALFOUNDRIES INC32016
KAPOOR SHAKTI32012–2014
HATTI SUNIL SURESH22012
Locations
LocationPatentsSpan
Bangalore, IN492010–2021
Karnataka, IN122009–2012
Banglaore, IN12019