Inventor
Jun-Bae Kim
Inventor
Seoul, KR
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores27%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses16%
H03KPulse technique9%
A61FFilters implantable into blood vessels4%
A61LMethods or apparatus for sterilising materials or objects in general4%
C08LCompositions of macromolecular compounds4%
A61HPhysical therapy apparatus, e.g. devices for locating or stimulating reflex points in the body2%
A61KPreparations for medical, dental or toiletry purposes2%
A63BApparatus for physical training, gymnastics, swimming, climbing, or fencing2%
B29CShaping or joining of plastics2%
PatentTitleYear
10,022,477Composition for anti-adhesion, surgical mesh composite with anti-adhesion property comprising the same and method for producing thereof20189,883,935'Process for preparing hernia mesh from monofilament'20189,379,693'Self bias buffer circuit and memory device including the same'20169,306,569'Compensation circuit for use with input buffer and method of operating the same'20168,730,751'Semiconductor memory device for controlling operation of delay-locked loop circuit'20148,542,045'Duty correcting circuit, delay-locked loop circuit and method of correcting duty'20138,324,928'Calibration circuit'20128,269,534'Delay locked loop circuit and semiconductor device having the delay locked loop circuit'20128,242,821'Delay-locked loop for correcting duty ratio of input clock signal and output clock signal and electronic device including the same'20128,237,476'Semiconductor memory device having delay lock loop with wide frequency range and delay cell current reduction scheme'20128,184,495'Semiconductor memory device for controlling operation of delay-locked loop circuit'20128,179,177'Wideband delay-locked loop (DLL) circuit'20128,054,117'Wideband delay-locked loop (DLL) circuit'20118,035,412'On-die termination latency clock control circuit and method of controlling the on-die termination latency clock'20117,969,182'Semiconductor devices having ZQ calibration circuits and calibration methods thereof'20117,936,196'First delay locking method, delay-locked loop, and semiconductor memory device including the same'20117,936,195'Wideband delay-locked loop (DLL) circuit'20117,823,031'Method and system for testing semiconductor memory device using internal clock signal of semiconductor memory device as data strobe signal'20107,696,626'Semiconductor device and method of arranging pad thereof'20107,554,371'Delay locked loop'20096,735,128'Data output driver of semiconductor memory device'20046,309,273'Hula hoop'2001D0447192'Hula hoop module'20015,379,081'Optical baffling device'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2018Based in Seoul, KR· patent location history
2009–2016Patents assigned to SAMSUNG ELECTRONICS CO LTD (18)· patent assignee history
2010Based in Dobong-gu, KR· patent location history
2012–2014Patents assigned to KIM JUN-BAE (6)· patent assignee history
2012Patents assigned to BAE CHANG-HYUN (2)· patent assignee history
2012–2014Patents assigned to CHANG YOUNG-UK (2)· patent assignee history
2012–2014Patents assigned to JANG SEONG-JIN (2)· patent assignee history
2018Based in Daejeon, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 18 | 2009–2016 |
| KIM JUN-BAEself | 6 | 2012–2014 |
| BAE CHANG-HYUN | 2 | 2012 |
| CHANG YOUNG-UK | 2 | 2012–2014 |
| JANG SEONG-JIN | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seoul, KR | 22 | 1995–2018 |
| Daejeon, KR | 1 | 2018 |
| Dobong-gu, KR | 1 | 2010 |