Inventor
Ariel Navon
Inventor
Revava, IL
Overview
Patents· 77 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing47%
G11CStatic stores26%
H03MCoding10%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
G06NComputing arrangements based on specific computational models4%
G11BInformation storage based on relative movement between record carrier and transducer2%
H04LTransmission of digital information, e.g. telegraphic communication2%
A45CPurses1%
A61BDiagnosis1%
H04KSecret communication1%
PatentTitleYear
11,086,804Storage system and method for reducing read-retry duration202111,068,165Non-volatile memory data write management202111,061,768Storage device with increased endurance202111,049,009Identifying memory block write endurance using machine learning202111,029,872Non-volatile storage system with data shaping memory partitions202111,023,138Management operations in predictable latency mode202111,023,380Non-volatile storage system with filtering of data samples for a monitored operational statistic202111,017,126Apparatus and method of detecting potential security violations of direct access non-volatile memory device202111,010,299System and method for performing discriminative predictive read202110,997,080Method and system for address table cache management based on correlation metric of first logical address and second logical address, wherein the correlation metric is incremented and decremented based on receive order of the first logical address and the second logical address202110,990,294Non-volatile storage system with multi-read mode202110,976,964Storage system and method for hit-rate-score-based selective prediction of future random read commands202110,977,179Solid state drive cache eviction policy by an unsupervised reinforcement learning scheme202110,938,421Decoding optimization for channel mismatch202110,929,309Direct host access to storage device memory space202110,922,235Method and system for address table eviction management202110,916,306Burst mode operation conditioning for a memory device202110,896,131System and method for configuring a storage device based on prediction of host source202110,891,052Adaptive system for optimization of non-volatile storage operational parameters202110,871,910Non-volatile memory with selective interleaved coding based on block reliability202010,866,740System and method for performance-based multiple namespace resource allocation in a memory202010,846,226System and method for prediction of random read commands in virtualized multi-queue memory systems202010,838,661Fast storage class memory using write once memory coding202010,802,908Data dependent allocation of error correction resources202010,795,827Adaptive management of intermediate storage202010,732,848System and method for predictive read of random data202010,732,871Storage device and method for adaptive sleep mode transitions202010,725,781System and method for chain prediction of multiple read commands202010,719,445System and method for scaling a historical pattern matching data structure in a memory device202010,712,949Adaptive device quality of service by host memory buffer range202010,649,776System and method for prediction of multiple read commands directed to non-sequential data202010,642,502System and method for prediction of read commands to non-sequential data202010,642,513Partially de-centralized latch management architectures for storage devices202010,613,778Dynamic host memory allocation to a memory controller202010,579,538Predicting addresses in non-volatile storage202010,554,227Decoding optimization for channel mismatch202010,503,586Dynamic read based on read statistics201910,474,525Soft bit techniques for a data storage device201910,459,844Managing flash memory read operations201910,409,676SRAM bit-flip protection with reduced overhead201910,382,067Parameterized iterative message passing decoder201910,379,940Pipeline delay detection during decoding by a data storage device201910,372,378Replacement data buffer pointers201910,372,373Adaptive power balancing for memory device operations201910,290,347Compacting operating parameter groups in solid state memory devices201910,289,341Operating parameter offsets in solid state memory devices201910,284,233ECC adjustment based on dynamic error information201910,275,186System and method of data compression and data shaping201910,250,281ECC decoder having adjustable parameters201910,223,199Non-volatile memory configured to return error reduced read data201910,191,799BER model evaluation201910,180,874Storage device operations based on bit error rate (BER) estimate201910,114,549Error correction code processing and data shaping for reducing wear to a memory201810,074,427Shaped data associated with an erase operation201810,061,349Head mountable camera system201810,002,265Storage system and method for providing gray levels of read security20189,947,401Peak current management in non-volatile storage20189,947,399Updating resistive memory20189,898,229'Systems and methods of memory reads'20189,875,156Data storage device with a memory die that includes an interleaver20189,865,360'Burn-in memory testing'20189,811,418'Syndrome-based codeword decoding'20179,734,009'Data encoding techniques for a device'20179,734,903'Disturb condition detection for a resistive random access memory'20179,697,905'Updating read voltages using syndrome weight comparisons'20179,583,196'Immediate feedback before or during programming'20179,583,183'Reading resistive random access memory based on leakage current'20179,484,089'Dual polarity read operation'20169,483,339'Systems and methods for fast bit error rate estimation'20169,312,002'Methods for programming ReRAM devices'20169,268,635'Error correction using multiple data sources'20169,135,155'Storage and retrieval of shaped data'20158,720,682'Holders for portable memory cards and methods for manufacturing same'20148,666,068'Method for scrambling shaped data'20148,645,810'Fast detection of convergence or divergence in iterative decoding'20148,301,979'Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders'20128,017,407'Device and method for monitoring blood parameters'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2014Patents assigned to NAVON ARIEL (5)· patent assignee history
2011–2014Based in Hod Hasharon, IL· patent location history
2012–2014Patents assigned to ALROD IDAN (3)· patent assignee history
2014–2018Patents assigned to SANDISK TECHNOLOGIES INC (15)· patent assignee history
2014–2021Based in Revava, IL· patent location history
2016–2020Patents assigned to SANDISK TECHNOLOGIES LLC (25)· patent assignee history
2019–2021Patents assigned to WESTERN DIGITAL TECH INC (44)· patent assignee history
2019Based in Revana, IL· patent location history
2021Based in San Jose, CA, US· patent location history
2021Based in Nahal Shilo, IL· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| WESTERN DIGITAL TECH INC | 44 | 2019–2021 |
| SANDISK TECHNOLOGIES LLC | 25 | 2016–2020 |
| SANDISK TECHNOLOGIES INC | 15 | 2014–2018 |
| NAVON ARIELself | 5 | 2011–2014 |
| ALROD IDAN | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Revava, IL | 71 | 2014–2021 |
| Hod Hasharon, IL | 2 | 2011–2014 |
| San Jose, California, US | 1 | 2021 |
| Nahal Shilo, IL | 1 | 2021 |
| Revana, IL | 1 | 2019 |