Inventor
Ruqiang BAO
Inventor
US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10DInorganic electric semiconductor devices30%
B82YSpecific uses or applications of nanostructures14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H10BElectronic memory devices2%
H10NElectric solid-state devices not otherwise provided for1%
G11CStatic stores1%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution1%
PatentTitleYear
12,575,145Monolithic stacked field effect transistor (SFET) with dual middle dielectric isolation (MDI) separation202612,568,806Conformal dielectric cap for subtractive vias202612,471,355Non-overlapping gate conductors for GAA transistors202512,446,306Stacked field effect transistor structure with independent gate control between top and bottom gates202512,433,020Multi-VT solution for replacement metal gate bonded stacked FET202512,402,408Stacked FETS including devices with thick gate oxide202512,317,555Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor202512,310,072Middle of line structure with stacked devices202512,310,100Dielectric reflow for boundary control202512,278,237Stacked FETS with non-shared work function metals202512,176,250Metal gate boundary for transistor scaling202412,176,348Self-aligned hybrid substrate stacked gate-all-around transistors202412,142,636Sidewall epitaxy encapsulation for nanosheet I/O device202412,107,168Independent gate length tunability for stacked transistors202412,068,387Multiple threshold voltage scheme in complementary metal oxide semiconductor transistors202412,034,005Self-aligned metal gate with poly silicide for vertical transport field-effect transistors202412,015,069Gate-all-around field effect transistor having multiple threshold voltages202411,961,895Gate stacks with multiple high-k dielectric layers202411,908,743Planar devices with consistent base dielectric202411,894,423Contact resistance reduction in nanosheet device structure202411,804,522Sidewall epitaxy encapsulation for nanosheet I/O device202311,749,744Fin structure for vertical transport field effect transistor202311,749,680Multi-threshold voltage non-planar complementary metal-oxide-semiconductor devices202311,735,593Gate stack dipole compensation for threshold voltage definition in transistors202311,710,521Static random-access memory cell design202311,688,635Oxygen-free replacement liner for improved transistor performance202311,605,634Multi-threshold voltage non-planar complementary metal-oxide-semiconductor devices202311,569,132Transistor structure with N/P boundary buffer202311,515,431Enabling residue free gap fill between nanosheets202211,476,418Phase change memory cell with a projection liner202211,456,415Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner202211,456,219Gate-all-around FETs having uniform threshold voltage202211,393,725Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device202211,329,136Enabling anneal for reliability improvement and multi-Vt with interfacial layer regrowth suppression202211,289,573Contact resistance reduction in nanosheet device structure202211,282,962Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)202211,282,838Stacked gate structures202211,276,767Additive core subtractive liner for metal cut etch processes202211,271,106Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts202211,257,721Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages202211,251,285Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices202211,245,020Gate-all-around field effect transistor having multiple threshold voltages202211,211,379Fabrication of field effect transistors with different threshold voltages through modified channel interfaces202111,195,762Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device202111,195,929Conformal replacement gate electrode for short channel devices202111,189,616Multi-threshold voltage non-planar complementary metal-oxtde-semiconductor devices202111,183,427Differing device characteristics on a single wafer by selective etch202111,177,257Fabrication of field effect transistors with different threshold voltages through modified channel interfaces202111,152,489Additive core subtractive liner for metal cut etch processes2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to IBM (49)· patent assignee history
2021Patents assigned to ULVAC INC (1)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 49 | 2021–2026 |
| ULVAC INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 49 | 2021–2026 |