Inventor
Luke England
Inventor
Saratoga Springs, NY, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
H01LSemiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10DInorganic electric semiconductor devices8%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H10HInorganic light-emitting semiconductor devices having potential barriers2%
H03KPulse technique1%
H05KPrinted circuits1%
B81BMicrostructural devices or systems, e.g. micromechanical devices1%
C23CCoating metallic material1%
PatentTitleYear
11,038,011Metal-insulator-metal capacitors including nanofibers202111,037,9063D IC package with RDL interposer and related method202110,818,570Stacked semiconductor devices having dissimilar-sized dies202010,770,440Micro-LED display assembly202010,741,460Methods for forming interconnect assemblies with probed bond pads202010,741,468Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods202010,636,776Methods of manufacturing RF filters202010,388,6313D IC package with RDL interposer and related method201910,381,304Interconnect structure201910,283,487Methods of forming integrated circuit package with thermally conductive pillar201910,236,263Methods and structures for mitigating ESD during wafer bonding201910,224,286Interconnect structure with adhesive dielectric layer and methods of forming same201910,193,011Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach201910,170,389Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods201910,163,864Vertically stacked wafers and methods of forming same201810,153,224Backside spacer structures for improved thermal performance201810,134,647Methods for forming interconnect assemblies with probed bond pads201810,090,227Back biasing in SOI FET technology201810,083,958Deep trench metal-insulator-metal capacitors201810,066,303Thin NiB or CoB capping layer for non-noble metallic bonding landing pads201810,069,490Method, apparatus and system for voltage compensation in a semiconductor wafer201810,026,883Wafer bond interconnect structures20189,865,570'Integrated circuit package with thermally conductive pillar'20189,716,487'Latency compensation network using timing slack sensors'20179,711,494'Methods of fabricating semiconductor die assemblies'20179,646,899'Interconnect assemblies with probed bond pads'20179,613,897'Integrated circuits including magnetic core inductors and methods for fabricating the same'20179,590,028'Method and device for an integrated trench capacitor'20179,553,058'Wafer backside redistribution layer warpage control'20179,553,080'Method and process for integration of TSV-middle in 3D IC stacks'20179,536,848'Bond pad structure for low temperature flip chip bonding'20179,466,659'Fabrication of multilayer circuit elements'20169,397,073'Method of using a back-end-of-line connection structure to distribute current envenly among multiple TSVs in a series for delivery to a top die'20169,379,091'Semiconductor die assemblies and semiconductor devices including same'20169,257,383'Method and device for an integrated trench capacitor'20169,153,520'Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods'20159,129,869'Pillar on pad interconnect structures, semiconductor devices including same and related methods'20158,937,309'Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication'20158,828,798'Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication'20148,659,153'Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods'20148,552,567'Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication'20138,421,168'Microelectromechanical systems microphone packaging systems'20138,304,888'Integrated circuit package with embedded components'20128,304,896'Embedded die package and process flow using a pre-molded carrier'20127,919,410'Packaging methods for imager devices'20117,863,096'Embedded die package and process flow using a pre-molded carrier'20117,622,786'EMI shielding for imager devices'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2012Based in Portland, ME, US· patent location history
2011–2013Patents assigned to FAIRCHILD SEMICONDUCTOR (4)· patent assignee history
2011–2019Based in Boise, ID, US· patent location history
2012–2013Patents assigned to ENGLAND LUKE (3)· patent assignee history
2013–2020Patents assigned to MICRON TECHNOLOGY INC (13)· patent assignee history
2013–2017Patents assigned to ENGLAND LUKE G (5)· patent assignee history
2014–2017Based in Tervuren, BE· patent location history
2016–2020Patents assigned to GLOBALFOUNDRIES INC (25)· patent assignee history
2016–2021Based in Saratoga Springs, NY, US· patent location history
2017–2020Based in Urbandale, IA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 25 | 2016–2020 |
| MICRON TECHNOLOGY INC | 13 | 2013–2020 |
| ENGLAND LUKE Gself | 5 | 2013–2017 |
| FAIRCHILD SEMICONDUCTOR | 4 | 2011–2013 |
| ENGLAND LUKEself | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Saratoga Springs, New York, US | 27 | 2016–2021 |
| Boise, ID, US | 7 | 2011–2019 |
| Tervuren, BE | 5 | 2014–2017 |
| Portland, ME, US | 4 | 2009–2012 |
| Urbandale, IA, US | 3 | 2017–2020 |