Inventor
Michael Danilenko
Inventor
West St. Paul, MN, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing71%
G05BControl or regulating systems in general14%
G11CStatic stores14%
PatentTitleYear
5,045,999'Multi-function timing sequencer for different speed main storage units'19914,930,106'Dual cache RAM for rapid invalidation'19904,736,292'Electronic data processing system overlaid jump mechanism'19884,691,279'Instruction buffer for a digital data processing system'19874,381,541'Buffer memory referencing system for two data words'19834,009,470'Pre-emptive, rotational priority system'1977Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1977Patents assigned to SPERRY RAND CORP (1)· patent assignee history
1977–1990Based in West St. Paul, MN, US· patent location history
1983Patents assigned to SPERRY CORP (1)· patent assignee history
1987–1991Patents assigned to UNISYS CORP (4)· patent assignee history
1988Based in St. Paul, MN, US· patent location history
1991Based in West Saint Paul, MN, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNISYS CORP | 4 | 1987–1991 |
| SPERRY CORP | 1 | 1983 |
| SPERRY RAND CORP | 1 | 1977 |
Locations
| Location | Patents | Span |
|---|---|---|
| West St. Paul, Minnesota, US | 4 | 1977–1990 |
| West Saint Paul, Minnesota, US | 1 | 1991 |
| St. Paul, Minnesota, US | 1 | 1988 |