Inventor
Kyoo-Chul Cho
Inventor
Yongin-si, KR
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H10DInorganic electric semiconductor devices15%
C23CCoating metallic material11%
C07FAcyclic, carbocyclic or heterocyclic compounds containing elements other than carbon, hydrogen, halogen, oxygen, nitrogen, sulfur, selenium or tellurium9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
Y10TTechnical subjects covered by former us classification6%
B82YSpecific uses or applications of nanostructures4%
C07CAcyclic or carbocyclic compounds4%
C30BSingle-crystal growth4%
PatentTitleYear
9,359,382'β-ketoimine ligand, method of preparing the same, metal complex comprising the same and method of forming thin film using the same'20169,359,383'β-ketoimine ligand, method of preparing the same, metal complex comprising the same and method of forming thin film using the same'20169,035,309'3D CMOS image sensors, sensor systems including the same'20158,268,397'Organometallic precursor, thin film having the same, metal wiring including the thin film, method of forming a thin film and method of manufacturing a metal wiring using the same'20127,964,907'Integrated circuit device gate structures'20117,675,091'Semiconductor wafer and method of fabricating the same'20107,648,854'Methods of forming metal oxide layers, methods of forming gate structures using the same, and methods of forming capacitors using the same'20107,573,123'Semiconductor device and method for forming the same'20097,550,347'Methods of forming integrated circuit device gate structures'20097,488,684'Organic aluminum precursor and method of forming a metal wire using the same'20097,452,569'Organic aluminum precursor and method of manufacturing a metal wiring using the same'20087,372,150'Semiconductor wafer having identification indication'20086,919,214'Apparatus for analyzing a substrate employing a copper decoration'20056,724,474'Wafer surface inspection method'20046,552,337'Methods and systems for measuring microroughness of a substrate combining particle counter and atomic force microscope measurements'20036,472,040'Semi-pure and pure monocrystalline silicon ingots and wafers'20026,170,235'Wafer packaging method'20016,045,610'Methods of manufacturing monocrystalline silicon ingots and wafers by controlling pull rate profiles in a hot zone furnance'20005,944,889'Methods of heat-treating semiconductor wafers'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2016Patents assigned to SAMSUNG ELECTRONICS CO LTD (19)· patent assignee history
1999–2003Based in Kyungki-do, KR· patent location history
2004–2005Based in Yongin, KR· patent location history
2008–2016Based in Yongin-si, KR· patent location history
2008–2011Based in Gyeonggi-do, KR· patent location history
2012–2015Patents assigned to CHO KYOO-CHUL (2)· patent assignee history
2012Patents assigned to CHO JUN-HYUN (1)· patent assignee history
2012Patents assigned to CHO YOUN-JOUNG (1)· patent assignee history
2016Patents assigned to ADEKA CORP (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 19 | 1999–2016 |
| ADEKA CORP | 2 | 2016 |
| CHO KYOO-CHULself | 2 | 2012–2015 |
| CHO JUN-HYUN | 1 | 2012 |
| CHO YOUN-JOUNG | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yongin-si, KR | 6 | 2008–2016 |
| Gyeonggi-do, KR | 6 | 2008–2011 |
| Kyungki-do, KR | 5 | 1999–2003 |
| Yongin, KR | 2 | 2004–2005 |