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Inventor

Mark Kiehlbauch

Inventor
Boise, ID, US

Overview

50→
Patents
2007–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 50 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10BElectronic memory devices18%
H10DInorganic electric semiconductor devices16%
H01LSemiconductor devices9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
Y10TTechnical subjects covered by former us classification5%
H01GCapacitors4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H01JElectric discharge tubes or discharge lamps4%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems3%
PatentTitleYear
10,879,247Semiconductor constructions, and semiconductor processing methods202010,553,607Method of forming an array of elevationally-extending strings of programmable memory cells and method of forming an array of elevationally-extending strings of memory cells202010,446,578Methods used in forming an array of elevationally-extending strings of memory cells, methods of forming an array of elevationally-extending strings of memory cells, and methods of forming an array of vertical strings of memory cells201910,014,301Semiconductor constructions20189,595,387'High aspect ratio openings'20179,443,756'Methods of forming a substrate opening'20169,224,798'Capacitor forming methods'20159,153,497'Semiconductor constructions'20159,090,460'Plasma processing with preionized and predissociated tuning gases and associated systems and methods'20159,005,463'Methods of forming a substrate opening'20159,005,473'Gaseous compositions comprising hydrogen fluoride and an alkylated ammonia derivative'20158,910,591'Apparatus and methods for capacitively coupled plasma vapor processing of semiconductor wafers'20148,853,050'Methods of forming capacitors'20148,772,166'Spacer process for on pitch contacts and related structures'20148,760,841'High aspect ratio openings'20148,759,228'Chemistry and compositions for manufacturing integrated circuits'20148,734,656'Capacitor forming methods'20148,721,836'Plasma processing with preionized and predissociated tuning gases and associated systems and methods'20148,696,922'Methods of plasma etching platinum-comprising materials, methods of processing semiconductor substrates in the fabrication of integrated circuitry, and methods of forming a plurality of memory cells'20148,623,725'Methods of forming capacitors'20148,614,151'Method of etching a high aspect ratio contact'20138,524,561'Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions'20138,512,582'Methods of patterning a substrate'20138,513,135'Methods of modifying oxide spacers'20138,507,380'Methods of forming contact openings and methods of increasing contact area in only one of X and Y axes in the fabrication of integrated circuitry'20138,500,913'Methods for treating surfaces, and methods for removing one or more materials from surfaces'20138,388,851'Capacitor forming methods'20138,375,890'Apparatus and methods for capacitively coupled plasma vapor processing of semiconductor wafers'20138,318,035'Methods of finishing quartz glass surfaces and components made by the methods'20128,274,777'High aspect ratio openings'20128,268,695'Methods of making capacitors'20128,252,194'Methods of removing silicon oxide'20128,241,987'Methods of forming capacitors'20128,211,803'Spacer process for on pitch contacts and related structures'20128,207,041'Semiconductor processing methods'20128,088,691'Selective etch chemistries for forming high aspect ratio features and associated structures'20128,039,399'Methods of forming patterns utilizing lithography and spacers'20118,034,687'Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions'20118,026,180'Methods of modifying oxide spacers'20117,977,727'Semiconductor constructions'20117,964,471'Methods of forming capacitors'20117,910,487'Reverse masking profile improvements in high aspect ratio etch'20117,824,986'Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions'20107,737,039'Spacer process for on pitch contacts and related structures'20107,696,056'Methods of forming capacitors'20107,670,905'Semiconductor processing methods, and methods of forming flash memory structures'20107,553,770'Reverse masking profile improvements in high aspect ratio etch'20097,517,804'Selective etch chemistries for forming high aspect ratio features and associated structures'20097,402,258'Methods of removing metal contaminants from a component for a plasma processing apparatus'20087,250,114'Methods of finishing quartz glass surfaces and components made by the methods'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2012Patents assigned to LAM RES CORP (3)· patent assignee history
2007–2012Based in Hayward, CA, US· patent location history
2008–2020Based in Boise, ID, US· patent location history
2009–2020Patents assigned to MICRON TECHNOLOGY INC (46)· patent assignee history
2012–2015Patents assigned to KIEHLBAUCH MARK (20)· patent assignee history
2012–2015Patents assigned to KIEHLBAUCH MARK W (5)· patent assignee history
2012–2014Patents assigned to SHEA KEVIN R (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC462009–2020
KIEHLBAUCH MARKself202012–2015
KIEHLBAUCH MARK Wself52012–2015
SHEA KEVIN R42012–2014
LAM RES CORP32007–2012
Locations
LocationPatentsSpan
Boise, ID, US482008–2020
Hayward, California, US22007–2012