Inventor
Xunyuan Zhang
Inventor
Albany, NY, US
Overview
Patents· 112 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H01LSemiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10DInorganic electric semiconductor devices11%
H10NElectric solid-state devices not otherwise provided for2%
C23CCoating metallic material2%
H05KPrinted circuits1%
H10BElectronic memory devices1%
C09GPolishing compositions1%
G11CStatic stores1%
PatentTitleYear
10,679,937Devices and methods of forming low resistivity noble metal interconnect202010,643,845Repaired mask structures and resultant underlying patterned structures202010,636,656Methods of protecting structure of integrated circuit from rework202010,636,698Skip via structures202010,627,720Overlay mark structures202010,629,428Metal insulator metal capacitor devices202010,573,593Metal interconnects for super (skip) via integration202010,553,478IC structure with interface liner and methods of forming same202010,546,854Methods of forming V0 structures for semiconductor devices by forming a protection layer with a non-uniform thickness202010,485,111Via and skip via structures2019RE047630Semiconductor device having a self-forming barrier layer at via bottom201910,366,919Fully aligned via in ground rule region201910,283,372Interconnects formed by a metal replacement process201910,283,608Low resistance contacts to source or drain region of transistor201910,276,689Method of forming a vertical field effect transistor (VFET) and a VFET structure201910,262,892Skip via structures201910,236,256Pre-spacer self-aligned cut formation201910,211,147Metal-insulator-metal capacitors with dielectric inner spacers201910,199,271Self-aligned metal wire on contact structure and method for forming same201910,199,261Via and skip via structures201910,199,264Self aligned interconnect structures201910,164,104Method to form air-gap spacers and air-gap spacer-containing structures201810,163,633Non-mandrel cut formation201810,157,833Via and skip via structures201810,109,526Etch profile control during skip via formation201810,109,490Cobalt interconnects formed by selective bottom-up fill201810,079,208IC structure with interface liner and methods of forming same201810,056,291Post spacer self-aligned cuts201810,056,292Self-aligned lithographic patterning201810,026,687Metal interconnects for super (skip) via integration201810,014,215Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps201810,014,297Methods of forming integrated circuit structure using extreme ultraviolet photolithography technique and related integrated circuit structure20189,984,919Inverted damascene interconnect structures20189,966,338Pre-spacer self-aligned cut formation20189,953,834Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines20189,941,278Method and apparatus for placing a gate contact inside an active region of a semiconductor20189,922,929'Self aligned interconnect structures'20189,911,604'Sidewall spacer pattern formation method'20189,859,217'Middle of the line (MOL) metal contacts'20189,859,120'Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines'20189,853,110Method of forming a gate contact structure for a semiconductor device20179,837,268Raised fin structures and methods of fabrication20179,831,174Devices and methods of forming low resistivity noble metal interconnect20179,831,124Interconnect structures20179,824,970'Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures'20179,824,921'Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps'20179,805,972'Skip via structures'20179,799,559'Methods employing sacrificial barrier layer for protection of vias during trench formation'20179,799,555'Cobalt interconnects covered by a metal cap'20179,721,889'Middle of the line (MOL) metal contacts'20179,666,791'Topological method to build self-aligned MTJ without a mask'20179,613,906'Integrated circuits including modified liners and methods for fabricating the same'20179,589,836'Methods of forming ruthenium conductive structures in a metallization layer'20179,570,394'Formation of IC structure with pair of unitary metal fins'20179,559,059'Methods of forming an improved via to contact interface by selective formation of a conductive capping layer'20179,553,017'Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures'20179,530,691'Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias'20169,466,530'Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer'20169,437,711'Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices'20169,425,280'Semiconductor device with low-K spacers'20169,412,660'Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure'20169,391,140'Raised fin structures and methods of fabrication'20169,373,542'Integrated circuits and methods for fabricating integrated circuits with improved contact structures'20169,343,406'Device having self-repair Cu barrier for solving barrier degradation due to Ru CMP'20169,318,436'Copper based nitride liner passivation layers for conductive copper structures'20169,299,745'Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same'20169,297,775'Combinatorial screening of metallic diffusion barriers'20169,287,213'Integrated circuits with improved contact structures'20169,275,874'Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal'20169,269,615'Multi-layer barrier layer for interconnect structure'20169,263,327'Minimizing void formation in semiconductor vias and trenches'20169,236,557'Magnetic tunnel junction between metal layers of a semiconductor device'20169,236,299'Methods of forming a metal cap layer on copper-based conductive structures on an integrated circuit device'20169,209,135'Method for reducing wettability of interconnect material at corner interface and device incorporating same'20159,190,260'Topological method to build self-aligned MTJ without a mask'20159,190,486'Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance'20159,190,323'Semiconductor devices with copper interconnects and methods for fabricating same'20159,177,858'Methods for fabricating integrated circuits including barrier layers for interconnect structures'20159,159,617'Structure and method of forming silicide on fins'20159,159,610'Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same'20159,093,401'Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein'20159,087,881'Electroless fill of trench in semiconductor structure'20159,076,846'Methods for fabricating integrated circuits using surface modification to selectively inhibit etching'20159,076,792'Multi-layer barrier layer stacks for interconnect structures'20159,076,816'Method and device for self-aligned contact on a non-recessed metal gate'20159,064,948'Methods of forming a semiconductor device with low-k spacers and the resulting device'20159,059,255'Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product'20159,054,052'Methods for integration of pore stuffing material'20159,040,421'Methods for fabricating integrated circuits with improved contact structures'20159,018,711'Selective growth of a work-function metal in a replacement metal gate of a semiconductor device'20158,980,740'Barrier layer conformality in copper interconnects'20158,962,478'Method to use self-repair Cu barrier to solve barrier degradation due to Ru CMP'20158,932,934'Methods of self-forming barrier integration with pore stuffed ULK material'20158,907,483'Semiconductor device having a self-forming barrier layer at via bottom'20148,889,549'Methods of forming conductive structures using a sacrificial liner layer'20148,883,020'Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein'20148,883,631'Methods of forming conductive structures using a sacrificial material during a metal hard mask removal process'20148,877,633'Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system'20148,859,419'Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device'20148,791,014'Methods of forming copper-based conductive structures on semiconductor devices'20148,772,158'Multi-layer barrier layer stacks for interconnect structures'20148,753,975'Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device'20148,728,931'Multi-layer barrier layer for interconnect structure'20148,722,534'Method for reducing wettability of interconnect material at corner interface and device incorporating same'20148,704,372'Integrated circuits and methods for processing integrated circuits with embedded features'20148,691,696'Methods for forming an integrated circuit with straightened recess profile'20148,673,766'Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition'20148,623,758'Subtractive metal multi-layer barrier layer for interconnect structure'20148,609,531'Methods of selectively forming ruthenium liner layer'20138,586,473'Methods for fabricating integrated circuits with ruthenium-lined copper'20138,517,769'Methods of forming copper-based conductive structures on an integrated circuit device'20138,431,482'Integrated circuits and methods for processing integrated circuits with embedded features'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2020Patents assigned to GLOBALFOUNDRIES INC (111)· patent assignee history
2013–2016Patents assigned to ZHANG XUNYUAN (10)· patent assignee history
2013–2015Patents assigned to GLOBAL FOUNDRIES INC (3)· patent assignee history
2013–2014Patents assigned to HE MING (3)· patent assignee history
2013–2020Based in Albany, NY, US· patent location history
2013–2019Based in Troy, NY, US· patent location history
2014–2015Patents assigned to KIM HOON (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 111 | 2013–2020 |
| ZHANG XUNYUANself | 10 | 2013–2016 |
| GLOBAL FOUNDRIES INC | 3 | 2013–2015 |
| HE MING | 3 | 2013–2014 |
| KIM HOON | 3 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Albany, New York, US | 102 | 2013–2020 |
| Troy, New York, US | 10 | 2013–2019 |