Inventor
Hun Teak Lee
Inventor
Ichon-shi, KR
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1072%
H01LSemiconductor devices16%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
B23KSoldering or unsoldering3%
H05KPrinted circuits3%
PatentTitleYear
9,997,468Integrated circuit packaging system with shielding and method of manufacturing thereof20189,693,455'Integrated circuit packaging system with plated copper posts and method of manufacture thereof'20179,385,100'Integrated circuit packaging system with surface treatment and method of manufacture thereof'20169,129,826'Epoxy bump for overhang die'20159,093,278'Method of manufacture of integrated circuit packaging system with plasma processing'20158,729,687'Stackable integrated circuit package system'20148,716,108'Integrated circuit packaging system with ultra-thin chip and method of manufacture thereof'20148,519,517'Semiconductor system with fine pitch lead fingers and method of manufacturing thereof'20138,410,594'Inter-stacking module system'20138,304,874'Stackable integrated circuit package system'20128,269,356'Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates'20128,256,660'Semiconductor package system with fine pitch lead fingers and method of manufacturing thereof'20128,129,263'Wire bond interconnection and method of manufacture thereof'20127,986,047'Wire bond interconnection'20117,909,233'Method of manufacturing a semiconductor package with fine pitch lead fingers'20117,863,737'Integrated circuit package system with wire bond pattern'20117,759,783'Integrated circuit package system employing thin profile techniques'20107,745,322'Wire bond interconnection'20107,731,078'Semiconductor system with fine pitch lead fingers'20107,652,382'Micro chip-scale-package system'20107,453,156'Wire bond interconnection'20087,407,080'Wire bond capillary tip'20087,298,052'Micro chip-scale-package system'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2015Patents assigned to STATS CHIPPAC LTD (15)· patent assignee history
2007–2013Based in Ichon-shi, KR· patent location history
2008–2012Patents assigned to CHIPPAC INC (5)· patent assignee history
2008–2015Based in Ichon-si, KR· patent location history
2012–2017Patents assigned to LEE HUN TEAK (10)· patent assignee history
2012–2015Patents assigned to JANG KI YOUN (3)· patent assignee history
2012–2015Patents assigned to KIM JONG KOOK (3)· patent assignee history
2014–2018Based in Seongnam-si, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| STATS CHIPPAC LTD | 15 | 2007–2015 |
| LEE HUN TEAKself | 10 | 2012–2017 |
| CHIPPAC INC | 5 | 2008–2012 |
| JANG KI YOUN | 3 | 2012–2015 |
| KIM JONG KOOK | 3 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ichon-shi, KR | 14 | 2007–2013 |
| Seongnam-si, KR | 6 | 2014–2018 |
| Ichon-si, KR | 3 | 2008–2015 |