Inventor
Hsien-Pin Hu
Inventor
Zhubei City, TW
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H01LSemiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
G01RMeasuring electric variables7%
H10DInorganic electric semiconductor devices7%
H01FMagnets3%
H05KPrinted circuits3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H10BElectronic memory devices1%
G06FElectric digital data processing1%
PatentTitleYear
10,770,365Package structures and methods of forming the same202010,734,295Interposer test structures and methods202010,665,4743D packages and methods for forming the same202010,663,512Testing of semiconductor chips with microbumps202010,535,633Chip package having die structures of different heights and method of forming same202010,515,906Forming large chips through stitching2019RE047709Forming grounded through-silicon vias in a semiconductor substrate201910,319,699Chip package having die structures of different heights201910,297,5503D IC architecture with interposer and interconnect structure for bonding dies201910,269,5843D packages and methods for forming the same201910,262,939Configurable routing for packaging applications201910,175,294Testing of semiconductor chips with microbumps201910,163,853Formation method of chip package201810,163,856Stacked integrated circuit structure and method of forming201810,153,222Package structures and methods of forming the same201810,090,213Interposer test structures and methods201810,014,252Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors20189,978,637Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs)20189,818,720'Structure and formation method for chip package'20179,806,058'Chip package having die structures of different heights and method of forming same'20179,741,669'Forming large chips through stitching'20179,691,840'Cylindrical embedded capacitors'20179,653,531'Methods of manufacturing a package'20179,627,223'Methods and apparatus of packaging with interposers'20179,618,572'Testing of semiconductor chips with microbumps'20179,589,857'Interposer test structures and methods'20179,530,730'Configurable routing for packaging applications'20169,462,692'Test structure and method of testing electrical characteristics of through vias'20169,385,079'Methods for forming stacked capacitors with fuse protection'20169,372,206'Testing of semiconductor chips with microbumps'20169,373,673'3-D inductor and transformer'20169,305,808'Methods and apparatus of packaging with interposers'20169,299,649'3D packages and methods for forming the same'20169,128,123'Interposer test structures and methods'20159,116,203'Testing of semiconductor chips with microbumps'20159,064,705'Methods and apparatus of packaging with interposers'20159,059,026'3-D inductor and transformer'20158,993,432'Test structure and method of testing electrical characteristics of through vias'20158,896,094'Methods and apparatus for inductors and transformers in packages'20148,896,089'Interposers for semiconductor devices and methods of manufacture thereof'20148,878,182'Probe pad design for 3DIC package yield analysis'20148,872,345'Forming grounded through-silicon vias in a semiconductor substrate'20148,797,057'Testing of semiconductor chips with microbumps'20148,759,150'Approach for bonding dies onto interposers'20148,693,163'Cylindrical embedded capacitors'20148,502,338'Through-substrate via waveguides'20138,471,358'3D inductor and transformer'20138,362,591'Integrated circuits and methods of forming the same'20138,319,349'Approach for bonding dies onto interposers'20128,105,875'Approach for bonding dies onto interposers'20127,117,460'Method for physical parameter extraction for transistor model'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (23)· patent assignee history
2006Based in Hsinchu, TW· patent location history
2012–2015Patents assigned to HU HSIEN-PIN (13)· patent assignee history
2012–2015Patents assigned to HOU SHANG-YUN (10)· patent assignee history
2012–2015Patents assigned to JENG SHIN-PUU (9)· patent assignee history
2012–2020Based in Zhubei City, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (29)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 29 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 23 | 2006–2016 |
| HU HSIEN-PINself | 13 | 2012–2015 |
| HOU SHANG-YUN | 10 | 2012–2015 |
| JENG SHIN-PUU | 9 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Zhubei City, TW | 50 | 2012–2020 |
| Hsinchu, TW | 1 | 2006 |