Inventor
Hee-Sung Kang
Inventor
Yongin-si, KR
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H01LSemiconductor devices8%
H10BElectronic memory devices8%
G06FElectric digital data processing2%
G11CStatic stores2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B22DCasting of metals1%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
10,497,749Electronic device20199,773,840'Semiconductor memory with reduced contact margin'20179,111,880'Method of forming a pattern in a semiconductor device and method of forming a gate using the same'20159,065,046'Semiconductor device and method for fabricating the same, and microprocessor, processor, system, data storage system and memory system including the semiconductor device'20159,035,319'Nitride semiconductor and fabricating method thereof'20158,952,423'Semiconductor device having decoupling capacitors and dummy transistors'20158,846,304'Method of forming a pattern in a semiconductor device and method of forming a gate using the same'20148,409,787'Method of forming a pattern in a semiconductor device and method of forming a gate using the same'20138,132,374'External wall panel unit for saving energy and external wall structure system using the same'20128,114,730'Shared contact structure, semiconductor device and method of fabricating the semiconductor device'20127,914,973'Method of forming a pattern in a semiconductor device and method of forming a gate using the same'20117,781,282'Shared contact structure, semiconductor device and method of fabricating the semiconductor device'20107,550,822'Dual-damascene metal wiring patterns for integrated circuit devices'20097,410,843'Methods for fabricating reduced floating body effect static random access memory cells'20087,364,987'Method for manufacturing semiconductor device'20087,348,636'CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof'20087,338,885'Alignment mark and method for manufacturing a semiconductor device having the same'20087,323,420'Method for manufacturing multi-thickness gate dielectric layer of semiconductor device'20087,285,831'CMOS device with improved performance and method of fabricating the same'20077,217,625'Method of fabricating a semiconductor device having a shallow source/drain region'20077,179,750'Method for manufacturing multi-thickness gate dielectric layer of semiconductor device'20077,179,714'Method of fabricating MOS transistor having fully silicided gate'20077,105,900'Reduced floating body effect static random access memory cells and methods for fabricating the same'20067,052,965'Methods of fabricating MOS field effect transistors with pocket regions using implant blocking patterns'20067,045,429'Method of manufacturing a semiconductor device'20066,902,959'Semiconductor device having junction diode and fabricating method therefor'20056,855,641'CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof'20056,812,111'Methods for fabricating MOS transistors with notched gate electrodes'20046,794,716'SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same'20046,717,209'Semiconductor device having junction diode and fabricating method therefor'20046,706,569'SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same'20046,703,280'SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same'20046,541,822'Method of manufacturing an SOI type semiconductor that can restrain floating body effect'20036,521,959'SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same'20036,498,370'SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2015Patents assigned to SAMSUNG ELECTRONICS CO LTD (29)· patent assignee history
2002–2008Based in Kumi-shi, KR· patent location history
2003–2008Based in Kyungki-do, KR· patent location history
2004–2008Based in Seongnam, KR· patent location history
2006–2015Based in Yongin-si, KR· patent location history
2007–2015Based in Seongnam-si, KR· patent location history
2012–2013Patents assigned to KANG HEE-SUNG (2)· patent assignee history
2012Patents assigned to BAEK SUNG JIN (1)· patent assignee history
2012Patents assigned to JEONG GI HONG (1)· patent assignee history
2015–2019Patents assigned to SK HYNIX INC (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 29 | 2002–2015 |
| SK HYNIX INC | 3 | 2015–2019 |
| KANG HEE-SUNGself | 2 | 2012–2013 |
| BAEK SUNG JIN | 1 | 2012 |
| JEONG GI HONG | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yongin-si, KR | 7 | 2006–2015 |
| Kumi-shi, KR | 6 | 2002–2008 |
| Seongnam-si, KR | 5 | 2007–2015 |
| Kyungki-do, KR | 4 | 2003–2008 |
| Seongnam, KR | 4 | 2004–2008 |