Inventor
Shyng-Tsong Chen
Inventor
Patterson, NY, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H01LSemiconductor devices12%
B24BMachines, devices, or processes for grinding or polishing9%
B24DTools for grinding, buffing or sharpening8%
H10BElectronic memory devices4%
H10NElectric solid-state devices not otherwise provided for4%
G06NComputing arrangements based on specific computational models2%
H04WWireless communication networks2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
10,672,984Resistive memory crossbar array compatible with Cu metallization202010,672,980Resistive memory crossbar array with top electrode inner spacers202010,381,563Resistive memory crossbar array compatible with Cu metallization201910,361,367Resistive memory crossbar array with top electrode inner spacers201910,157,789Via formation using sidewall image transfer process to define lateral dimension20189,508,647'Single damascene interconnect structure'20169,490,168'Via formation using sidewall image transfer process to define lateral dimension'20169,224,686'Single damascene interconnect structure'20159,105,641'Profile control in interconnect structures'20158,835,305'Method of fabricating a profile control in interconnect structures'20148,835,326'Titanium-nitride removal'20148,754,520'Formation of air gap with protection of metal lines'20148,716,133'Three photomask sidewall image transfer method'20148,519,540'Self-aligned dual damascene BEOL structures with patternable low- K material and methods of forming same'20138,450,854'Interconnect structures with patternable low-k dielectrics and method of fabricating same'20138,415,248'Self-aligned dual damascene BEOL structures with patternable low-k material and methods of forming same'20138,399,350'Formation of air gap with protection of metal lines'20138,232,195'Method for fabricating back end of the line structures with liner and seed materials'20128,084,862'Interconnect structures with patternable low-k dielectrics and method of fabricating same'20117,892,968'Via gouging methods and related semiconductor structure'20117,838,428'Method of repairing process induced dielectric damage by the use of GCIB surface treatment using gas clusters of organic molecular species'20107,816,253'Surface treatment of inter-layer dielectric'20107,745,324'Interconnect with recessed dielectric adjacent a noble metal cap'20107,709,344'Integrated circuit fabrication process using gas cluster ion beam etching'20107,671,470'Enhanced mechanical strength via contacts'20107,670,943'Enhanced mechanical strength via contacts'20107,666,753'Metal capping process for BEOL interconnect with air gaps'20107,514,361'Selective thin metal cap process'20097,479,869'Metal resistor and resistor material'20097,439,624'Enhanced mechanical strength via contacts'20087,402,883'Back end of the line structures with liner and noble metal layer'20087,358,182'Method of forming an interconnect structure'20087,314,786'Metal resistor, resistor material and method'20087,253,098'Maintaining uniform CMP hard mask thickness'20077,190,079'Selective capping of copper wiring'20077,186,166'Fiber embedded polishing pad'20077,084,479'Line level air gaps'20067,064,064'Copper recess process with application to selective capping and electroless plating'20067,008,871'Selective capping of copper wiring'20066,989,117'Polishing pads with polymer filled fibrous web, and methods for fabricating and using same'20066,975,032'Copper recess process with application to selective capping and electroless plating'20056,964,604'Fiber embedded polishing pad'20056,734,096'Fine-pitch device lithography using a sacrificial hardmask'20046,712,681'Polishing pads with polymer filled fibrous web, and methods for fabricating and using same'20046,685,548'Grooved polishing pads and methods of use'20046,656,019'Grooved polishing pads and methods of use'20036,383,066'Multilayered polishing pad, method for fabricating, and use thereof'20026,340,325'Polishing pad grooving method and apparatus'20026,267,659'Stacked polish pad'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2020Patents assigned to IBM (47)· patent assignee history
2001–2015Based in Patterson, NY, US· patent location history
2004–2007Patents assigned to FREUDENBERG NONWOVENS LTD (3)· patent assignee history
2009–2020Based in Rensselaer, NY, US· patent location history
2011–2014Patents assigned to CHEN SHYNG-TSONG (9)· patent assignee history
2011–2013Patents assigned to LIN QINGHUANG (4)· patent assignee history
2012–2014Patents assigned to PONOTH SHOM (3)· patent assignee history
2013Based in Albany, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 47 | 2001–2020 |
| CHEN SHYNG-TSONGself | 9 | 2011–2014 |
| LIN QINGHUANG | 4 | 2011–2013 |
| FREUDENBERG NONWOVENS LTD | 3 | 2004–2007 |
| PONOTH SHOM | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Patterson, New York, US | 32 | 2001–2015 |
| Rensselaer, New York, US | 15 | 2009–2020 |
| Albany, New York, US | 2 | 2013 |