Inventor

Emre Alptekin

Inventor

Wappingers Falls, NY, US

Overview

2012–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices31%

H01LSemiconductor devices26%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%

H10BElectronic memory devices2%

B82YSpecific uses or applications of nanostructures1%

G06FElectric digital data processing0%

PatentTitleYear

10,943,988Thermally stable salicide formation for salicide first contacts2021 10,937,889Forming thermally stable salicide for salicide first contacts2021 10,818,759Self aligned replacement metal source/drain finFET2020 10,707,167Contacts to semiconductor substrate and methods of forming same2020 10,700,065Leakage current reduction in electrical isolation gate structures2020 10,693,005Reliable gate contacts over active areas2020 10,546,941Forming thermally stable salicide for salicide first contacts2020 10,453,935Thermally stable salicide formation for salicide first contacts2019 10,418,450Self aligned replacement metal source/drain finFET2019 10,381,480Reliable gate contacts over active areas2019 10,326,000FinFET with reduced parasitic capacitance2019 10,236,344Tunnel transistors with abrupt junctions2019 10,170,581FinFET with reduced parasitic capacitance2019 10,121,789Self-aligned source/drain contacts2018 10,103,226Method of fabricating tunnel transistors with abrupt junctions2018 10,083,865Partial spacer for increasing self aligned contact process margins2018 9,997,411Formation of metal resistor and e-fuse2018 9,985,104Contact first replacement metal gate2018 9,985,109FinFET with reduced parasitic capacitance2018 9,929,047'Partial spacer for increasing self aligned contact process margins'2018 9,865,546'Contacts to semiconductor substrate and methods of forming same'2018 9,818,873'Forming stressed epitaxial layers between gates separated by different pitches'2017 9,691,658'Contact fill in an integrated circuit'2017 9,679,993'Fin end spacer for preventing merger of raised active regions'2017 9,647,124'Semiconductor devices with graphene nanoribbons'2017 9,601,380'Fin end spacer for preventing merger of raised active regions'2017 9,576,957'Self-aligned source/drain contacts'2017 9,553,157'Diffusion-controlled oxygen depletion of semiconductor contact interface'2017 9,530,684'Method and structure to suppress finFET heating'2016 9,515,168'Fin end spacer for preventing merger of raised active regions'2016 9,514,992'Unidirectional spacer in trench silicide'2016 9,496,368'Partial spacer for increasing self aligned contact process margins'2016 9,496,362'Contact first replacement metal gate'2016 9,472,406'Metal semiconductor alloy contact resistance improvement'2016 9,472,415'Directional chemical oxide etch technique'2016 9,466,693'Self aligned replacement metal source/drain finFET'2016 9,449,827'Metal semiconductor alloy contact resistance improvement'2016 9,443,772'Diffusion-controlled semiconductor contact creation'2016 9,431,399'Method for forming merged contact for semiconductor device'2016 9,397,175'Multi-composition gate dielectric field effect transistors'2016 9,397,181'Diffusion-controlled oxygen depletion of semiconductor contact interface'2016 9,391,175'Fin end spacer for preventing merger of raised active regions'2016 9,390,928'Anisotropic dielectric material gate spacer for a field effect transistor'2016 9,379,012'Oxide mediated epitaxial nickel disilicide alloy contact formation'2016 9,368,493'Method and structure to suppress FinFET heating'2016 9,349,836'Fin end spacer for preventing merger of raised active regions'2016 9,337,041'Anisotropic dielectric material gate spacer for a field effect transistor'2016 9,331,166'Selective dielectric spacer deposition for exposing sidewalls of a finFET'2016 9,318,323'Semiconductor devices with graphene nanoribbons'2016 9,312,185'Formation of metal resistor and e-fuse'2016 9,305,835'Formation of air-gap spacer in transistor'2016 9,263,454'Semiconductor structure having buried conductive elements'2016 9,245,892'Semiconductor structure having buried conductive elements'2016 9,236,345'Oxide mediated epitaxial nickel disilicide alloy contact formation'2016 9,231,072'Multi-composition gate dielectric field effect transistors'2016 9,190,406'Fin field effect transistors having heteroepitaxial channels'2015 9,111,962'Selective dielectric spacer deposition for exposing sidewalls of a finFET'2015 9,059,290'FinFET device formation'2015 9,059,308'Method of manufacturing dummy gates of a different material as insulation between adjacent devices'2015 9,034,755'Method of epitaxially forming contact structures for semiconductor transistors'2015 8,999,799'Maskless dual silicide contact formation'2015 8,946,081'Method for cleaning semiconductor substrate'2015 8,927,422'Raised silicide contact'2015 8,927,375'Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level'2015 8,853,862'Contact structures for semiconductor transistors'2014 8,815,693'FinFET device formation'2014 8,796,099'Inducing channel strain via encapsulated silicide formation'2014 8,652,914'Two-step silicide formation'2014 8,652,963'MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture'2014 8,647,954'Two-step silicide formation'2014 8,643,122'Silicide contacts having different shapes on regions of a semiconductor device'2014 8,629,510'Two-step silicide formation'2014 8,603,915'Multi-stage silicidation process'2013 8,603,881'Raised trench metal semiconductor alloy formation'2013 8,492,275'Method to form uniform silicide by selective implantation'2013 8,415,250'Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device'2013 8,298,895'Selective threshold voltage implants for long channel devices'2012

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2012–2021Patents assigned to IBM (63)· patent assignee history

2012–2018Patents assigned to ALPTEKIN EMRE (11)· patent assignee history

2012–2021Based in Wappingers Falls, NY, US· patent location history

2013–2020Patents assigned to GLOBALFOUNDRIES INC (16)· patent assignee history

2013–2015Patents assigned to SARDESAI VIRAJ YASHAWANT (3)· patent assignee history

2013–2014Patents assigned to TRAN CUNG D (3)· patent assignee history

2014–2020Based in Fishkill, NY, US· patent location history

2020Based in Santa Clara, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	63	2012–2021
GLOBALFOUNDRIES INC	16	2013–2020
ALPTEKIN EMREself	11	2012–2018
SARDESAI VIRAJ YASHAWANT	3	2013–2015
TRAN CUNG D	3	2013–2014

Locations

Location	Patents	Span
Wappingers Falls, New York, US	55	2012–2021
Fishkill, New York, US	21	2014–2020
Santa Clara, California, US	1	2020