Inventor

James K. Pickett

Inventor

Austin, TX, US

Overview

52→

Patents

1988–2018

Patent span

Physics

Primary field (CPC G)

Patents· 52 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing91%

G11CStatic stores4%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%

G01RMeasuring electric variables2%

PatentTitleYear

10,163,508Supporting multiple memory types in a memory slot2018 7,836,259'Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy'2010 7,415,597'Processor with dependence mechanism to predict whether a load is dependent on older store'2008 7,363,470'System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor'2008 7,321,964'Store-to-load forwarding buffer using indexed lookup'2008 7,266,673'Speculation pointers to identify data-speculative operations in microprocessor'2007 7,251,710'Cache memory subsystem including a fixed latency R/W pipeline'2007 7,222,226'System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation'2007 7,165,167'Load store unit with replay mechanism'2007 7,133,969'System and method for handling exceptional instructions in a trace cache based processor'2006 7,089,400'Data speculation based on stack-relative addressing patterns'2006 7,043,626'Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming'2006 7,028,166'System and method for linking speculative results of load operations to register values'2006 7,024,537'Data speculation based on addressing patterns identifying dual-purpose register'2006 6,957,319'Integrated circuit with multiple microcode ROMs'2005 6,957,322'Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion'2005 6,944,744'Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor'2005 6,845,442'System and method of using speculative operand sources in order to speculatively bypass load-store operations'2005 6,826,704'Microprocessor employing a performance throttling mechanism for power management'2004 6,438,664'Microcode patch device and method for patching microcode using match registers and patch routines'2002 6,298,424'Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation'2001 6,202,139'Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing'2001 6,175,908'Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte'2001 6,151,662'Data transaction typing for improved caching and prefetching characteristics'2000 6,141,745'Functional bit identifying a prefix byte via a particular state regardless of type of instruction'2000 6,106,573'Apparatus and method for tracing microprocessor instructions'2000 6,101,595'Fetching instructions from an instruction cache using sequential way prediction'2000 6,088,781'Stride instruction for fetching data separated by a stride amount'2000 6,079,006'Stride-based data address prediction structure'2000 6,076,156'Instruction redefinition using model specific registers'2000 6,073,230'Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches'2000 6,058,461'Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation'2000 5,968,169'Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses'1999 5,958,045'Start of access instruction configured to indicate an access mode for fetching memory operands in a microprocessor'1999 5,940,876'Stride instruction for fetching data separated by a stride amount'1999 5,933,626'Apparatus and method for tracing microprocessor instructions'1999 5,933,618'Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction'1999 5,926,646'Context-dependent memory-mapped registers for transparent expansion of a register file'1999 5,893,146'Cache structure having a reduced tag comparison to enable data transfer from said cache'1999 5,892,936'Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register'1999 5,872,943'Apparatus for aligning instructions using predecoded shift amounts'1999 5,854,921'Stride-based data address prediction structure'1998 5,848,433'Way prediction unit and a method for operating the same'1998 5,845,323'Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time'1998 5,832,297'Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations'1998 5,764,946'Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address'1998 5,761,712'Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array'1998 5,752,069'Superscalar microprocessor employing away prediction structure'1998 5,664,167'Microprogrammed timer processor having a variable loop resolution architecture'1997 5,339,395'Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode'1994 4,797,650'CMOS binary equals comparator with carry in and out'1989 4,755,696'CMOS binary threshold comparator'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–1997Patents assigned to DELCO ELECTRONICS CORP (4)· patent assignee history

1988–1994Based in Kokomo, IN, US· patent location history

1997–2018Based in Austin, TX, US· patent location history

1998–2010Patents assigned to ADVANCED MICRO DEVICES INC (47)· patent assignee history

2018Patents assigned to INTEL CORP (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	47	1998–2010
DELCO ELECTRONICS CORP	4	1988–1997
INTEL CORP	1	2018

Locations

Location	Patents	Span
Austin, Texas, US	49	1997–2018
Kokomo, IN, US	3	1988–1994